SBAS590E March   2016  – June 2020 ADS131A02 , ADS131A04

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Asynchronous Interrupt Interface Mode
    7. 7.7  Switching Characteristics: Asynchronous Interrupt Interface Mode
    8. 7.8  Timing Requirements: Synchronous Master Interface Mode
    9. 7.9  Switching Characteristics: Synchronous Master Interface Mode
    10. 7.10 Timing Requirements: Synchronous Slave Interface Mode
    11. 7.11 Switching Characteristics: Synchronous Slave Interface Mode
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Clock
        1. 9.3.1.1 XTAL1/CLKIN and XTAL2
        2. 9.3.1.2 ICLK
        3. 9.3.1.3 MODCLK
        4. 9.3.1.4 Data Rate
      2. 9.3.2 Analog Input
      3. 9.3.3 Input Overrange and Underrange Detection
      4. 9.3.4 Reference
      5. 9.3.5 ΔΣ Modulator
      6. 9.3.6 Digital Decimation Filter
      7. 9.3.7 Watchdog Timer
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low-Power and High-Resolution Mode
      2. 9.4.2 Power-Up
      3. 9.4.3 Standby and Wake-Up Mode
      4. 9.4.4 Conversion Mode
      5. 9.4.5 Reset (RESET)
    5. 9.5 Programming
      1. 9.5.1 Interface Protocol
        1. 9.5.1.1 Device Word Length
        2. 9.5.1.2 Fixed versus Dynamic-Frame Mode
        3. 9.5.1.3 Command Word
        4. 9.5.1.4 Status Word
        5. 9.5.1.5 Data Words
          1. 9.5.1.5.1 ADC Data Word 16-Bit Format
          2. 9.5.1.5.2 ADC Data Word 24-Bit Format
        6. 9.5.1.6 Hamming Code Error Correction
        7. 9.5.1.7 Cyclic Redundancy Check (CRC)
          1. 9.5.1.7.1 Computing the CRC
          2. 9.5.1.7.2 CRC With CRC_MODE = 1
          3. 9.5.1.7.3 CRC with CRC_MODE = 0
          4. 9.5.1.7.4 CRC Using the WREGS Command
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Asynchronous Interrupt Mode
          1. 9.5.2.1.1 Chip Select (CS)
          2. 9.5.2.1.2 Serial Clock (SCLK)
          3. 9.5.2.1.3 Data Input (DIN)
          4. 9.5.2.1.4 Data Output (DOUT)
          5. 9.5.2.1.5 Data Ready (DRDY)
          6. 9.5.2.1.6 Asynchronous Interrupt Mode Data Retrieval
        2. 9.5.2.2 Synchronous Master Mode
          1. 9.5.2.2.1 Serial Clock (SCLK)
          2. 9.5.2.2.2 Data Input (DIN)
          3. 9.5.2.2.3 Data Output (DOUT)
          4. 9.5.2.2.4 Data Ready (DRDY)
          5. 9.5.2.2.5 Chip Select (CS)
          6. 9.5.2.2.6 Synchronous Master Mode Data Retrieval
        3. 9.5.2.3 Synchronous Slave Mode
          1. 9.5.2.3.1 Chip Select (CS)
          2. 9.5.2.3.2 Serial Clock (SCLK)
          3. 9.5.2.3.3 Data Input (DIN)
          4. 9.5.2.3.4 Data Output (DOUT)
          5. 9.5.2.3.5 Data Ready (DRDY)
          6. 9.5.2.3.6 Synchronous Slave Mode Data Retrieval
        4. 9.5.2.4 ADC Frame Complete (DONE)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  NULL: Null Command
        2. 9.5.3.2  RESET: Reset to POR Values
        3. 9.5.3.3  STANDBY: Enter Standby Mode
        4. 9.5.3.4  WAKEUP: Exit Standby Mode
        5. 9.5.3.5  LOCK: Lock ADC Registers
        6. 9.5.3.6  UNLOCK: Unlock ADC Registers
          1. 9.5.3.6.1 UNLOCK from POR or RESET
        7. 9.5.3.7  RREG: Read a Single Register
        8. 9.5.3.8  RREGS: Read Multiple Registers
        9. 9.5.3.9  WREG: Write Single Register
        10. 9.5.3.10 WREGS: Write Multiple Registers
    6. 9.6 Register Maps
      1. 9.6.1 User Register Description
        1. 9.6.1.1  ID_MSB: ID Control Register MSB (address = 00h) [reset = xxh]
          1. Table 16. ID_MSB Register Field Descriptions
        2. 9.6.1.2  ID_LSB: ID Control Register LSB (address = 01h) [reset = xxh]
          1. Table 17. ID_LSB Register Field Descriptions
        3. 9.6.1.3  STAT_1: Status 1 Register (address = 02h) [reset = 00h]
          1. Table 18. STAT_1 Register Field Descriptions
        4. 9.6.1.4  STAT_P: Positive Input Fault Detect Status Register (address = 03h) [reset = 00h]
          1. Table 19. STAT_P Register Field Descriptions
        5. 9.6.1.5  STAT_N: Negative Input Fault Detect Status Register (address = 04h) [reset = 00h]
          1. Table 20. STAT_N Register Field Descriptions
        6. 9.6.1.6  STAT_S: SPI Status Register (address = 05h) [reset = 00h]
          1. Table 21. STAT_S Register Field Descriptions
        7. 9.6.1.7  ERROR_CNT: Error Count Register (address = 06h) [reset = 00h]
          1. Table 22. ERROR_CNT Register Field Descriptions
        8. 9.6.1.8  STAT_M2: Hardware Mode Pin Status Register (address = 07h) [reset = xxh]
          1. Table 23. STAT_M2 Register Field Descriptions
        9. 9.6.1.9  Reserved Registers (address = 08h to 0Ah) [reset = 00h]
          1. Table 24. Reserved Registers Field Descriptions
        10. 9.6.1.10 A_SYS_CFG: Analog System Configuration Register (address = 0Bh) [reset = 60h]
          1. Table 25. A_SYS_CFG Register Field Descriptions
        11. 9.6.1.11 D_SYS_CFG: Digital System Configuration Register (address = 0Ch) [reset = 3Ch]
          1. Table 27. D_SYS_CFG Register Field Descriptions
        12. 9.6.1.12 CLK1: Clock Configuration 1 Register (address = 0Dh) [reset = 08h]
          1. Table 28. CLK1 Register Field Descriptions
        13. 9.6.1.13 CLK2: Clock Configuration 2 Register (address = 0Eh) [reset = 86h]
          1. Table 29. CLK2 Register Field Descriptions
        14. 9.6.1.14 ADC_ENA: ADC Channel Enable Register (address = 0Fh) [reset = 00h]
          1. Table 31. ADC_ENA Register Field Descriptions
        15. 9.6.1.15 Reserved Register (address = 10h) [reset = 00h]
          1. Table 32. Reserved Register Field Descriptions
      2. 9.6.2 ADCx: ADC Channel Digital Gain Configuration Registers (address = 11h to 14h) [reset = 00h]
        1. Table 33. ADCx Registers Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Power Monitoring Specific Applications
      3. 10.1.3 Multiple Device Configuration
        1. 10.1.3.1 First Device Configured in Asynchronous Interrupt Mode
        2. 10.1.3.2 First Device Configured in Synchronous Master Mode
        3. 10.1.3.3 All Devices Configured in Synchronous Slave Mode
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 What To Do and What Not To Do
    4. 10.4 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Negative Charge Pump
    2. 11.2 Internal Digital LDO
    3. 11.3 Power-Supply Sequencing
    4. 11.4 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PBS|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C. Typical specifications are at TA = 25°C; all specifications are at IOVDD = 3.3 V, AVDD = 2.5 V, AVSS = –2.5 V, VNCPEN (register 0Bh, bit 7) = 0, internal VREF = 2.442 V, fCLKIN = 16.384 MHz, fMOD = 4.096 MHz, data rate = 8 kSPS, and gain = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Cs Input capacitance 3.5 pF
Zin Differential input impedance fMOD = 4.096 MHz 130 kΩ
ADC PERFORMANCE
Resolution 24 Bits
Gain 1, 2, 4, 8, 16
Data rate fMOD = 4.096 MHz 1 128 kSPS
DC PERFORMANCE
Dynamic range 105 111 dB
AVDD – AVSS = 5 V, VREF = 4 V, VNCPEN bit = 0 115
All other settings See Noise Measurements section
INL Integral nonlinearity Best fit 8 20 ppm
Offset error 500 µV
Offset drift 2.5 4 µV/°C
Gain error Excluding voltage reference and reference buffer error ±0.03 % of FS
Gain drift Excluding voltage reference and reference buffer error 0.5 2 ppm/°C
AC PERFORMANCE
CMRR Common-mode rejection ratio fCM = 50 Hz or 60 Hz 100 dB
PSRR Power-supply rejection ratio AVDD supply, fPS = 50 Hz and 60 Hz 80 dB
IOVDD supply, fPS = 50 Hz and 60 Hz 105
Crosstalk fIN = 50 Hz and 60 Hz –125 dB
SNR Signal-to-noise ratio fIN = 50 Hz or 60 Hz, VREF = 2.442 V, VIN = –20 dBFS, normalized 111 dB
fIN = 50 Hz or 60 Hz, VREF = 4.0 V, VIN = –20 dBFS, normalized 115
THD Total harmonic distortion fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS, ADS131A02 –101.5 dB
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS, ADS131A04 –103.5
SINAD Signal-to-noise + distortion fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS 101 dB
SFDR Spurious-free dynamic range fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS, ADS131A02 102.5 dB
fIN = 50 Hz or 60 Hz (up to 50 harmonics), VIN = –0.5 dBFS, ADS131A04 105
EXTERNAL REFERENCE
Reference buffer offset TA = 25°C 250 µV
Reference buffer offset drift –40°C ≤ TA ≤ +125°C 4 7 µV/°C
REFEXT input impedance 50 MΩ
INTERNAL REFERENCE VOLTAGE (REFP – REFN)
VREF Reference output voltage VREF_4V bit = 0 2.442 V
VREF_4V bit = 1, AVDD – AVSS > 4.5 V 4.0
Accuracy ±0.1%
Temperature drift Including reference buffer drift, –40°C ≤ TA ≤ +125°C 6 20 ppm/°C
Start-up time REFEXT = 1-µF to AVSS, settled to 1% 0.2 ms
REFEXT = 1-µF to AVSS, settled to 0.1% 1.2
REFEXT = 1-µF to AVSS, settled to 0.01% 250
REFP source capability 100 µA
EXTERNAL CLOCK SOURCE
fICLK Internal ICLK frequency (SCLK output in master mode) CLKSRC bit = 0 0.2 8.192 12.5 MHz
fMOD ADC modulator frequency High-resolution mode VNCPEN bit = 0 0.1 4.096 4.25 MHz
VNCPEN bit = 1 0.512 4.096 4.25
Low-power mode VNCPEN bit = 0 0.1 1.024 1.05
VNCPEN bit = 1 0.512 1.024 1.05
DIGITAL INPUT/OUTPUT
VIH High-level input voltage 0.8 IOVDD IOVDD V
VIL Low-level input voltage GND 0.2 IOVDD V
VOH High-level output voltage IOH = 1 mA 0.8 IOVDD V
VOL Low-level output voltage IOL = –1 mA 0.2 IOVDD V
IIN Input current 0 V < VDigital Input < IOVDD –10 10 μA
POWER-SUPPLY
VNCP Negative charge pump output voltage –2 –1.65 V
AVDD current ADS131A02, high-resolution mode AVDD = 3.3 V, AVSS = 0 V, negative charge pump enabled 3.2 mA
Negative charge pump disabled 3 3.75
ADS131A04, high-resolution mode AVDD = 3.3 V, AVSS = 0 V, negative charge pump enabled 4
Negative charge pump disabled 4 4.7
ADS131A02, low-power mode 0.9
ADS131A04, low-power mode 1.1
IOVDD current ADS131A02, high-resolution mode AVDD = 3.3 V, AVSS = 0 V, negative charge pump enabled 0.6 mA
Negative charge pump disabled 0.6 0.8
ADS131A04, high-resolution mode AVDD = 3.3 V, AVSS = 0 V, negative charge pump enabled 0.8
Negative charge pump disabled 0.8 1.0
ADS131A02, low-power mode 0.5
ADS131A04, low-power mode 0.5
Power dissipation ADS131A02, high-resolution mode AVDD = 3.3 V, AVSS = 0 V, negative charge pump enabled 12.5 mW
Negative charge pump disabled 17 21
ADS131A04, high-resolution mode AVDD = 3.3 V, AVSS = 0 V, negative charge pump enabled 15.8
Negative charge pump disabled 22.7 26.8
ADS131A02, low-power mode AVDD = 3.3 V, AVSS = 0 V, negative charge pump enabled 4.6
Negative charge pump disabled 6.5
ADS131A04, low-power mode AVDD = 3.3 V, AVSS = 0 V, negative charge pump enabled 5.3
Negative charge pump disabled 7.2
Standby mode, fCLKIN = 16.384 MHz 2.6