SBAS705B June   2015  – April 2020 ADS131E08S

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Power Application: Three-Phase Voltage and Current Connection
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Electromagnetic Interference (EMI) Filter
      2. 9.3.2  Input Multiplexer
        1. 9.3.2.1 Device Noise Measurements
        2. 9.3.2.2 Test Signals (TestP and TestN)
        3. 9.3.2.3 Temperature Sensor (TempP, TempN)
        4. 9.3.2.4 Power-Supply Measurements (MVDDP, MVDDN)
      3. 9.3.3  Analog Input
      4. 9.3.4  PGA Settings and Input Range
        1. 9.3.4.1 Input Common-Mode Range
      5. 9.3.5  ΔΣ Modulator
      6. 9.3.6  Clock
      7. 9.3.7  Digital Decimation Filter
      8. 9.3.8  Voltage Reference
      9. 9.3.9  Input Out-of-Range Detection
      10. 9.3.10 General-Purpose Digital I/O (GPIO)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down
      2. 9.4.2 Reset
      3. 9.4.3 Conversion Mode
        1. 9.4.3.1 START Pin Low-to-High Transition or START Command Sent
        2. 9.4.3.2 Input Signal Step
        3. 9.4.3.3 Continuous Conversion Mode
    5. 9.5 Programming
      1. 9.5.1 SPI Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output (DOUT)
        5. 9.5.1.5 Data Ready (DRDY)
      2. 9.5.2 Data Retrieval
        1. 9.5.2.1 Status Word
        2. 9.5.2.2 Readback Length
        3. 9.5.2.3 Data Format
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  WAKEUP: Exit STANDBY Mode
        2. 9.5.3.2  STANDBY: Enter STANDBY Mode
        3. 9.5.3.3  RESET: Reset Registers to Default Values
        4. 9.5.3.4  START: Start Conversions
        5. 9.5.3.5  STOP: Stop Conversions
        6. 9.5.3.6  OFFSETCAL: Channel Offset Calibration
        7. 9.5.3.7  RDATAC: Start Read Data Continuous Mode
        8. 9.5.3.8  SDATAC: Stop Read Data Continuous Mode
        9. 9.5.3.9  RDATA: Read Data
        10. 9.5.3.10 RREG: Read from Register
        11. 9.5.3.11 WREG: Write to Register
        12. 9.5.3.12 Sending Multibyte Commands
    6. 9.6 Register Map
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h) [reset = D2h]
          1. Table 11. ID: ID Control Register Field Descriptions
        2. 9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) [reset = 94h]
          1. Table 12. CONFIG1: Configuration Register 1 Field Descriptions
        3. 9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) [reset = 00h]
          1. Table 14. CONFIG2: Configuration Register 2 Field Descriptions
        4. 9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) [reset = E0h]
          1. Table 15. CONFIG3: Configuration Register 3 Field Descriptions
        5. 9.6.1.5 FAULT: Fault Detect Control Register (address = 04h) [reset = 00h]
          1. Table 16. FAULT: Fault Detect Control Register Field Descriptions
        6. 9.6.1.6 CHnSET: Individual Channel Settings (address = 05h to 0Ch) [reset = 10h]
          1. Table 17. CHnSET: Individual Channel Settings Field Descriptions
        7. 9.6.1.7 FAULT_STATP: Fault Detect Positive Input Status (address = 12h) [reset = 00h]
          1. Table 18. FAULT_STATP: Fault Detect Positive Input Status Field Descriptions
        8. 9.6.1.8 FAULT_STATN: Fault Detect Negative Input Status (address = 13h) [reset = 00h]
          1. Table 19. FAULT_STATN: Fault Detect Negative Input Status Field Descriptions
        9. 9.6.1.9 GPIO: General-Purpose IO Register (address = 14h) [reset = 0Fh]
          1. Table 20. GPIO: General-Purpose IO Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Multiple Device Configuration
        1. 10.1.1.1 Synchronizing Multiple Devices
        2. 10.1.1.2 Standard Configuration
        3. 10.1.1.3 Daisy-Chain Configuration
      2. 10.1.2 Power Monitoring Specific Applications
      3. 10.1.3 Current Sensing
      4. 10.1.4 Voltage Sensing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Initialization Set Up
      1. 10.3.1 Setting the Device Up for Basic Data Capture
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Timing
    2. 11.2 Recommended External Capacitor Values
    3. 11.3 Device Connections for Unipolar Power Supplies
    4. 11.4 Device Connections for Bipolar Power Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.2 Detailed Design Procedure

The line voltage is stepped down to a voltage range within the measurable range of the ADC. The reference voltage determines the range in which the ADC can measure signals. The ADS131E08S has two integrated low-drift reference voltage options: 2.4 V and 4 V.

Equation 11 describes the transfer function for the voltage divider at the input in Figure 60. Using multiple series resistors, RDIV1, and multiple parallel resistors, RDIV2, allows for power and heat to be dissipated among several circuit elements and serves as protection against a potential short-circuit across a single resistor. The number of resistors trade off with nominal accuracy because each additional element introduces an additional source of tolerance.

Equation 11. ADS131E08S eq_apps_Vdiv_sbas705.gif

The step-down resistor, RDiv2, dominates the measurement error produced by the resistor network. Using input PGAs on the ADS131E08S helps to mitigate this error source by allowing RDiv2 to be made smaller and then amplifying the signal to near full-scale using the ADS131E08S PGA.

For this design, RDiv1 is set to 200 kΩ and RDiv2 is set to 2.4 kΩ to provide proper signal attenuation at a sufficient power level across each resistor. The input saturates at values greater than ±750 V when using the ADS131E08S internal 2.4-V reference and a PGA gain of 2.

The ADS131E08S measures the line current by creating a voltage across the burden resistance (RBurden in Figure 60) in parallel with the secondary winding of a CT. As with the voltage measurement front-end, multiple resistors (RDiv1) that are used to step down a voltage share the duty of dissipating power. In this design, RBURDEN is set to 33 Ω. Used with a 1:500 turns ratio CT, the ADC input saturates with a line current over 25 A when the ADC is configured using the internal 2.4-V reference and a PGA gain of 2.

Diodes protect the ADS131E08S inputs from overvoltage and current. Diodes on each input shunt to either supply if the input voltage exceeds the safe range for the device. On current inputs, a diode shunts the inputs if current on the secondary winding of the CT threatens to damage the device.

The combination of RFilt, CCom, and CDif form the antialiasing filters for each of the inputs. The differential capacitor CDif improves the common-mode rejection of the system by sharing its tolerance between the positive and negative input. The antialiasing filter requirement is not strict because the nature of a ΔΣ converter (with oversampling and digital filter) attenuates a significant proportion of out-of-band noise. In addition, the input PGAs have intentionally low bandwidth to provide additional antialiasing. The component values used in this design are RFilt = 1 kΩ, CCom = 47 pF, and CDif = 0.015 μF. This first-order filter produces a relatively flat frequency response beyond 2 kHz, capable of measuring greater than 30 harmonics at a 50-Hz or 60-Hz fundamental frequency. The 3-dB cutoff frequency of the filter is 5.3 kHz for each input channel.

The ETU in a circuit breaker or protection relay can be powered from the line. In this case, fast power-up is required to allow the ADC to begin making measurements shortly after power is restored. The ADS131E08S is designed to fully power-up and collect data in less than 3 ms.

Each analog system block introduces errors from input to output. Protection CTs in the 5P accuracy class can introduce as much as ±1% current error from input to output. CTs in the 10P accuracy class can introduce as much as ±3% error. The burden resistor also introduces errors in the form of resistor tolerance and temperature drift. For the voltage input, error comes from the divider network in the form of resistor tolerance and temperature drift. Finally, the converter introduces errors in the form of offset error, gain error, and reference error. All of these specifications can drift over temperature.