SBAS621B July   2013  – September 2015 ADS42JB46

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS42JB46
    6. 7.6  Electrical Characteristics: General
    7. 7.7  Timing Characteristics
    8. 7.8  Digital Characteristics
    9. 7.9  Reset Timing
    10. 7.10 Serial Interface Timing
    11. 7.11 Typical Characteristics: ADS42JB46
    12. 7.12 Typical Characteristics: Contour
      1. 7.12.1 Spurious-Free Dynamic Range (SFDR)
      2. 7.12.2 Signal-to-Noise Ratio (SNR)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Gain
      2. 8.3.2 Overrange Indication
      3. 8.3.3 Input Clock Divider
      4. 8.3.4 Pin Controls
    4. 8.4 Device Functional Modes
      1. 8.4.1 JESD204B Interface
        1. 8.4.1.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.1.2 JESD204B Test Patterns
        3. 8.4.1.3 JESD204B Frame Assembly
        4. 8.4.1.4 JESD Link Configuration
          1. 8.4.1.4.1 Configuration for 2-Lane (20x) SERDES Mode
          2. 8.4.1.4.2 Configuration for 4-Lane (10x) SERDES Mode
        5. 8.4.1.5 CML Outputs
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Register Initialization
        2. 8.5.1.2 Serial Register Write
        3. 8.5.1.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Summary of Serial Interface Registers
      2. 8.6.2 Description of Serial Interface Registers
        1. 8.6.2.1  Register Address 06
        2. 8.6.2.2  Register Address 07
        3. 8.6.2.3  Register Address 08
        4. 8.6.2.4  Register Address 0B
        5. 8.6.2.5  Register Address 0C
        6. 8.6.2.6  Register Address 0D
        7. 8.6.2.7  Register Address 0E
        8. 8.6.2.8  Register Address 0F
        9. 8.6.2.9  Register Address 10
        10. 8.6.2.10 Register Address 11
        11. 8.6.2.11 Register Address 12
        12. 8.6.2.12 Register Address 13
        13. 8.6.2.13 Register Address 1F
        14. 8.6.2.14 Register Address 26
        15. 8.6.2.15 Register Address 27
        16. 8.6.2.16 Register Address 2B
        17. 8.6.2.17 Register Address 2C
        18. 8.6.2.18 Register Address 2D
        19. 8.6.2.19 Register Address 30
        20. 8.6.2.20 Register Address 36
        21. 8.6.2.21 Register Address 37
        22. 8.6.2.22 Register Address 38
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
          1. 9.2.2.1.1 Drive Circuit Requirements
          2. 9.2.2.1.2 Driving Circuit
        2. 9.2.2.2 Clock Input
        3. 9.2.2.3 SNR and Clock Jitter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RGC Package
64-Pin VQFN
Top View
ADS42JB46 po2_las900.gif

Pin Functions: JESD204B Output Interface

PIN I/O FUNCTION DESCRIPTION
NAME NO.
AGND 12, 15, 19, 20, 23, 26, 28, 34, 37 I Supply Analog ground
AVDD 11, 16, 18, 22, 27, 31, 33, 38, 40 I Supply 1.8-V analog power supply
AVDD3V 17, 32 I Supply 3.3-V analog supply for analog buffer
CLKINM 24 I Clock Differential ADC clock input (negative)
CLKINP 25 I Clock Differential ADC clock input (positive)
CTRL1 39 I Control Power-down control with an internal 150-kΩ pull-down resistor
CTRL2 10 I Control Power-down control with an internal 150-kΩ pull-down resistor
DA0M 53 O Interface JESD204B serial data output for channel A, lane 0 (negative)
DA0P 54 O Interface JESD204B serial data output for channel A, lane 0 (positive)
DA1M 51 O Interface JESD204B serial data output for channel A, lane 1 (negative)
DA1P 52 O Interface JESD204B serial data output for channel A, lane 1 (positive)
DB0M 57 O Interface JESD204B serial data output for channel B, lane 0 (negative)
DB0P 56 O Interface JESD204B serial data output for channel B, lane 0 (positive)
DB1M 59 O Interface JESD204B serial data output for channel B, lane 1 (negative)
DB1P 58 O Interface JESD204B serial data output for channel B, lane 1 (positive)
DGND 1, 3, 46, 48, 50, 63 I Supply Digital ground
DRVDD 2, 7, 47, 49, 60, 64 I Supply Digital 1.8-V power supply
INAM 35 I Input Differential analog input for channel A (negative)
INAP 36 I Input Differential analog input for channel A (positive)
INBM 14 I Input Differential analog input for channel B (negative)
INBP 13 I Input Differential analog input for channel B (positive)
IOVDD 55 I Supply Digital 1.8-V power supply for the JESD204B transmitter
MODE 4 I Control Connect to GND
OVRA 61 O Interface Overrange indication for channel A in CMOS output format
OVRB 62 O Interface Overrange indication for channel B in CMOS output format
PDN_GBL 6 I Control Global power-down. Active high with an internal 150-kΩ pull-down resistor.
RESET 44 I Control Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor.
SCLK 43 I Control Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
SDATA 42 I Control Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
SDOUT 45 O Control Serial interface data output
SEN 41 I Control Serial interface enable. This pin has an internal 150-kΩ pull-up resistor.
STBY 5 I Control Standby. Active high with an internal 150-kΩ pull-down resistor.
SYNC~M 8 I Interface Synchronization input for JESD204B port (negative)
SYNC~P 9 I Interface Synchronization input for JESD204B port (positive)
SYSREFM 30 I Clock External SYSREF input, subclass 1 (negative)
SYSREFP 29 I Clock External SYSREF input, subclass 1 (positive)
VCM 21 O Output 1.9-V common-mode output voltage for analog inputs
Thermal Pad 65 GND Ground Connect to ground plane