Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter (ADC)


Product details


Sample rate (Max) (MSPS) 160 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 2.5 Power consumption (Typ) (mW) 1360 Architecture Pipeline SNR (dB) 75.2 ENOB (Bits) 12 SFDR (dB) 100 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGC) 64 81 mm² 9 x 9 open-in-new Find other High-speed ADCs (>10MSPS)


  • Dual-Channel ADCs
  • 14-Bit Resolution
  • Maximum Clock Rate: 160 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two- and Four-Lane Support
  • Analog Input Buffer with High-Impedance
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm QFN-64
  • Power Dissipation: 679 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 72.9 dBFS
      • SFDR: 90 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.2 dBFS
      • SFDR: 84 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3
open-in-new Find other High-speed ADCs (>10MSPS)


The ADS42JB46 is a high-linearity, dual-channel, 14-bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

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Type Title Date
* Data sheet ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter datasheet (Rev. B) Sep. 02, 2015
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
Technical article How to achieve fast frequency hopping Mar. 03, 2019
Technical article RF sampling: Learning more about latency Feb. 09, 2017
User guide ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation Module User's Guide (Rev. D) Feb. 08, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note Correcting the Low-Frequency Response of the ADS42LBxx, ADS42JBxx for Time-Domai May 02, 2016
User guide TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) Jan. 11, 2016
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) Mar. 19, 2015
User guide Interoperability of TI ADS42JB69 Family of JESD204B ADCs with Altera FPGAs Oct. 04, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The ADS42JB46EVM is an evaluation module (EVM) that allows for the evaluation of the ADS42JB46 and LMK04828 clock jitter cleaner. ADS42JB46 is a low-power, 14-bit, 160-MSPS analog-to-digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface. The EVM has (...)

  • Flexible transformer-coupled analog input to allow for variety of sources and frequencies
  • Easy-to-use software GUI to configure ADS42JB46 and LMK04828 for variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High-Speed Data Converter Pro Software (...)

Software development

JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
SLAC544D.ZIP (162552 KB)
High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
  • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SBAM174.ZIP (174 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RGC) 64 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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