Product details

Sample rate (Max) (MSPS) 160 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 2.5 Power consumption (Typ) (mW) 1360 Architecture Pipeline SNR (dB) 75.2 ENOB (Bits) 12 SFDR (dB) 100 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 160 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 2.5 Power consumption (Typ) (mW) 1360 Architecture Pipeline SNR (dB) 75.2 ENOB (Bits) 12 SFDR (dB) 100 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFN (RGC) 64 81 mm² 9 x 9
  • Dual-Channel ADCs
  • 14-Bit Resolution
  • Maximum Clock Rate: 160 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two- and Four-Lane Support
  • Analog Input Buffer with High-Impedance
    Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm QFN-64
  • Power Dissipation: 679 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 72.9 dBFS
      • SFDR: 90 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.2 dBFS
      • SFDR: 84 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3
  • Dual-Channel ADCs
  • 14-Bit Resolution
  • Maximum Clock Rate: 160 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two- and Four-Lane Support
  • Analog Input Buffer with High-Impedance
    Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm QFN-64
  • Power Dissipation: 679 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 72.9 dBFS
      • SFDR: 90 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.2 dBFS
      • SFDR: 84 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3

The ADS42JB46 is a high-linearity, dual-channel, 14-bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

The ADS42JB46 is a high-linearity, dual-channel, 14-bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

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Technical documentation

Design & development

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Evaluation board

ADS42JB46EVM — ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter Evaluation Module

The ADS42JB46EVM is an evaluation module (EVM) that allows for the evaluation of the ADS42JB46 and LMK04828 clock jitter cleaner. ADS42JB46 is a low-power, 14-bit, 160-MSPS analog-to-digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface. The EVM has (...)

Not available on TI.com
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
GUI for evaluation module (EVM)

ADS42JBxx GUI v1p1 installer (Rev. D)

SLAC544D.ZIP (162552 KB)
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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADS42JB46 IBIS Model ADS42JB46 IBIS Model

Simulation tool

PSPICE-FOR-TI PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RGC) 64 View options

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