SBAS621B July   2013  – September 2015 ADS42JB46

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS42JB46
    6. 7.6  Electrical Characteristics: General
    7. 7.7  Timing Characteristics
    8. 7.8  Digital Characteristics
    9. 7.9  Reset Timing
    10. 7.10 Serial Interface Timing
    11. 7.11 Typical Characteristics: ADS42JB46
    12. 7.12 Typical Characteristics: Contour
      1. 7.12.1 Spurious-Free Dynamic Range (SFDR)
      2. 7.12.2 Signal-to-Noise Ratio (SNR)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Gain
      2. 8.3.2 Overrange Indication
      3. 8.3.3 Input Clock Divider
      4. 8.3.4 Pin Controls
    4. 8.4 Device Functional Modes
      1. 8.4.1 JESD204B Interface
        1. 8.4.1.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.1.2 JESD204B Test Patterns
        3. 8.4.1.3 JESD204B Frame Assembly
        4. 8.4.1.4 JESD Link Configuration
          1. 8.4.1.4.1 Configuration for 2-Lane (20x) SERDES Mode
          2. 8.4.1.4.2 Configuration for 4-Lane (10x) SERDES Mode
        5. 8.4.1.5 CML Outputs
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Register Initialization
        2. 8.5.1.2 Serial Register Write
        3. 8.5.1.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Summary of Serial Interface Registers
      2. 8.6.2 Description of Serial Interface Registers
        1. 8.6.2.1  Register Address 06
        2. 8.6.2.2  Register Address 07
        3. 8.6.2.3  Register Address 08
        4. 8.6.2.4  Register Address 0B
        5. 8.6.2.5  Register Address 0C
        6. 8.6.2.6  Register Address 0D
        7. 8.6.2.7  Register Address 0E
        8. 8.6.2.8  Register Address 0F
        9. 8.6.2.9  Register Address 10
        10. 8.6.2.10 Register Address 11
        11. 8.6.2.11 Register Address 12
        12. 8.6.2.12 Register Address 13
        13. 8.6.2.13 Register Address 1F
        14. 8.6.2.14 Register Address 26
        15. 8.6.2.15 Register Address 27
        16. 8.6.2.16 Register Address 2B
        17. 8.6.2.17 Register Address 2C
        18. 8.6.2.18 Register Address 2D
        19. 8.6.2.19 Register Address 30
        20. 8.6.2.20 Register Address 36
        21. 8.6.2.21 Register Address 37
        22. 8.6.2.22 Register Address 38
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
          1. 9.2.2.1.1 Drive Circuit Requirements
          2. 9.2.2.1.2 Driving Circuit
        2. 9.2.2.2 Clock Input
        3. 9.2.2.3 SNR and Clock Jitter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range, unless otherwise noted.(1)
MIN MAX UNIT
Supply voltage AVDD3V –0.3 3.6 V
AVDD –0.3 2.1 V
DRVDD –0.3 2.1 V
IOVDD –0.3 2.1 V
Voltage between AGND and DGND –0.3 0.3 V
Voltage applied to input pins INAP, INBP, INAM, INBM –0.3 3 V
CLKINP, CLKINM –0.3 minimum (2.1, AVDD + 0.3) V
SYNC~P, SYNC~M –0.3 minimum (2.1, AVDD + 0.3) V
SYSREFP, SYSREFM –0.3 minimum (2.1, AVDD + 0.3) V
SCLK, SEN, SDATA, RESET, PDN_GBL, CTRL1, CTRL2, STBY, MODE –0.3 3.9 V
Temperature Operating free-air, TA –40 85 °C
Operating junction, TJ 125 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions(3)

Over operating free-air temperature range, unless otherwise noted.
MIN NOM MAX UNIT
SUPPLIES
AVDD Analog supply voltage 1.7 1.8 1.9 V
AVDD3V Analog buffer supply voltage 3.15 3.3 3.45 V
DRVDD Digital supply voltage 1.7 1.8 1.9 V
IOVDD Output buffer supply voltage 1.7 1.8 1.9 V
ANALOG INPUTS
VID Differential input voltage range Default after reset 2 VPP
Register programmable(1) 2.5 VPP
VICR Input common-mode voltage VCM ± 0.025 V
Maximum analog input frequency with 2.5-VPP input amplitude 250 MHz
Maximum analog input frequency with 2-VPP input amplitude 400 MHz
CLOCK INPUT
Input clock sample rate 10x mode 60 160 MSPS
20x mode 40 156.25 MSPS
Input clock amplitude differential
(VCLKP – VCLKM)		 Sine wave, ac-coupled 0.3(2) 1.5 VPP
LVPECL, ac-coupled 1.6 VPP
LVDS, ac-coupled 0.7 VPP
LVCMOS, single-ended, ac-coupled 1.5 V
Input clock duty cycle 35% 50% 65%
DIGITAL OUTPUTS
CLOAD Maximum external load capacitance from each output pin to DRGND 3.3 pF
RLOAD Single-ended load resistance +50 Ω
TA Operating free-air temperature –40 85 °C
(1) For details, refer to the Digital Gain section.
(2) Refer to the Performance vs Clock Amplitude curves (Figure 32 and Figure 33).
(3) To reset the device for the first time after power-up, only use the RESET pin. Refer to the Register Initialization section.

7.4 Thermal Information

THERMAL METRIC(1) ADS42JB46 UNIT
RGC (QFN)
64 PINS
RθJA Junction-to-ambient thermal resistance 22.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 7.1 °C/W
RθJB Junction-to-board thermal resistance 2.5 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 2.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: ADS42JB46

Typical values are at TA = 25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and sampling clock rate = 160 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V.
PARAMETER TEST CONDITIONS 2-VPP FULL-SCALE 2.5-VPP FULL-SCALE UNIT
MIN TYP MAX MIN TYP MAX
SNR Signal-to-noise ratio fIN = 10 MHz 73.7 75.2 dBFS
fIN = 70 MHz 73.5 74.9 dBFS
fIN = 170 MHz 69.5 72.9 74.2 dBFS
fIN = 230 MHz 72.3 73.3 dBFS
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz 73.5 75.1 dBFS
fIN = 70 MHz 73.3 74.7 dBFS
fIN = 170 MHz 68.5 72.8 73.6 dBFS
fIN = 230 MHz 72 72.8 dBFS
SFDR Spurious-free dynamic range
(including second and third harmonic distortion)		 fIN = 10 MHz 96 92 dBc
fIN = 70 MHz 94 90 dBc
fIN = 170 MHz 79 90 84 dBc
fIN = 230 MHz 86 83 dBc
THD Total harmonic distortion fIN = 10 MHz 93 90 dBc
fIN = 70 MHz 91 88 dBc
fIN = 170 MHz 76 87 82 dBc
fIN = 230 MHz 84 81 dBc
HD2 2nd-order harmonic distortion fIN = 10 MHz 96 95 dBc
fIN = 70 MHz 94 90 dBc
fIN = 170 MHz 79 92 89 dBc
fIN = 230 MHz 88 86 dBc
HD3 3rd-order harmonic distortion fIN = 10 MHz 97 92 dBc
fIN = 70 MHz 96 94 dBc
fIN = 170 MHz 79 90 84 dBc
fIN = 230 MHz 86 83 dBc
Worst spur
(other than second and third harmonics)		 fIN = 10 MHz 102 101 dBc
fIN = 70 MHz 102 100 dBc
fIN = 170 MHz 87 100 95 dBc
fIN = 230 MHz 98 92 dBc
IMD Two-tone intermodulation distortion f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS		 97 95 dBFS
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS		 90 89 dBFS
Crosstalk 20-MHz, full-scale signal on channel under observation;
170-MHz, full-scale signal on other channel		 100 100 dB
Input overload recovery Recovery to within 1% (of full-scale) for 6-dB overload with sine-wave input 1 1 Clock cycle
PSRR AC power-supply rejection ratio For a 90-mVPP signal on AVDD supply, up to 10 MHz > 40 > 40 dB
ENOB Effective number of bits fIN = 170 MHz 11.8 12 LSBs
DNL Differential nonlinearity fIN = 170 MHz ±0.4 ±0.5 LSBs
INL Integrated nonlinearity fIN = 170 MHz ±0.75 ±3 ±0.9 LSBs

7.6 Electrical Characteristics: General

Typical values are at 25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, , and sampling clock rate = 160 MSPS unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
VID Differential input voltage range Default (after reset) 2 VPP
Register programmed(1) 2.5 VPP
Differential input resistance (at 170 MHz) 1.2 kΩ
Differential input capacitance (at 170 MHz) 4 pF
Analog input bandwidth With 50-Ω source impedance and 50-Ω termination 900 MHz
VCM Common-mode output voltage 1.9 V
VCM output current capability 10 mA
DC ACCURACY
Offset error –20 20 mV
EGREF Gain error as a result of internal reference inaccuracy alone –2 2 %FS
EGCHAN Gain error of channel alone –5 %FS
Temperature coefficient of EGCHAN 0.01 Δ%/°C
POWER SUPPLY
IAVDD Analog supply current 90 130 mA
IAVDD3V Analog buffer supply current 234 330 mA
IDRVDD Digital supply current 174 207 mA
IOVDD Output buffer supply current 50-Ω external termination from pin to IOVDD, fIN = 2.5 MHz, 10x mode 61 100 mA
Analog power 162 mW
Analog buffer power 772 mW
Digital power 313 mW
Power consumption by output buffer 50-Ω external termination from pin to IOVDD, fIN = 2.5 MHz, 10x mode 109 mW
Total power 1.36 1.64 W
Global power-down 160 mW
(1) Refer to the Serial Interface section.

7.7 Timing Characteristics

Typical values are at 25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, and sampling clock rate = 160 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V. See Figure 3.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAMPLE TIMING CHARACTERISTICS
Aperture delay 0.4 0.7 1.1 ns
Aperture delay matching Between two channels on the same device ±70 ps
Between two devices at the same temperature and supply voltage ±150 ps
Aperture jitter 85 fS rms
Wake-up time Time to valid data after exiting STANDBY mode 50 200 µs
Time to valid data after exiting global power-down 250 1000 µs
tSU_SYNC~ Setup time for SYNC~ Referenced to input clock rising edge 400 ps
tH_SYNC~ Hold time for SYNC~ Referenced to input clock rising edge 100 ps
tSU_SYSREF Setup time for SYSREF Referenced to input clock rising edge 400 ps
tH_SYSREF Hold time for SYSREF Referenced to input clock rising edge 100 ps
CML OUTPUT TIMING CHARACTERISTICS
Unit interval 320 1667 ps
Serial output data rate 3.125 Gbps
TJitter Total jitter 1.6 Gbps (10x mode, fS = 160 MSPS) 0.28 P-PUI
3.125 Gbps (20x mode, fS = 156.25 MSPS) 0.3 P-PUI
tR, tF Data rise time,
data fall time		 Rise and fall times are measured from 20% to 80%,
differential output waveform,
600 Mbps ≤ bit rate ≤ 3.125 Gbps		 105 ps

7.8 Digital Characteristics

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and IOVDD = 1.8 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE)(1)
VIH High-level input voltage All digital inputs support 1.8-V and 3.3-V
logic levels		 1.2 V
VIL Low-level input voltage All digital inputs support 1.8-V and 3.3-V
logic levels		 0.4 V
IIH High-level input current SEN 0 µA
RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE 10 µA
IIL Low-level input current SEN 10 µA
RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, MODE 0 µA
DIGITAL INPUTS (SYNC~P, SYNC~M, SYSREFP, SYSREFM)
VIH High-level input voltage 1.3 V
VIL Low-level input voltage 0.5 V
VCM_DIG Input common-mode voltage 0.9 V
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB)
VOH High-level output voltage DRVDD – 0.1 DRVDD V
VOL Low-level output voltage 0.1 V
DIGITAL OUTPUTS (JESD204B Interface: DA[0,1], DB[0,1])(2)
VOH High-level output voltage IOVDD V
VOL Low-level output voltage IOVDD – 0.4 V
|VOD| Output differential voltage 0.4 V
VOCM Output common-mode voltage IOVDD – 0.2 V
Transmitter short-circuit current Transmitter terminals shorted to any voltage between –0.25 V and 1.45 V –100 100 mA
Single-ended output impedance 50 Ω
COUT Output capacitance Output capacitance inside the device,
from either output to ground		 2 pF
(1) The RESET, SCLK, SDATA, PDN_GBL, STBY, CTRL1, CTRL2, and MODE pins have a 150-kΩ (typical) internal pulldown resistor to ground. The SEN pin has a 150-kΩ (typical) pullup resistor to AVDD.
(2) 50-Ω, single-ended, external termination to IOVDD.

7.9 Reset Timing (1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 Power-on delay Delay from AVDD and DRVDD power-up to active RESET pulse 1 ms
t2 Reset pulse width Active RESET signal pulse width 10 ns
1 µs
t3 Register write delay Delay from RESET disable to SEN active 100 ns
(1) Typical values are at 25°C and minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C, unless otherwise noted.

7.10 Serial Interface Timing(1)

PARAMETER MIN TYP MAX UNIT
fSCLK SCLK frequency (equal to 1 / tSCLK) > dc 20 MHz
tSLOADS SEN to SCLK setup time 25 ns
tSLOADH SCLK to SEN hold time 25 ns
tDSU SDIO setup time 25 ns
tDH SDIO hold time 25 ns
(1) Typical values are at 25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C, AVDD3V = 3.3 V, and AVDD = DRVDD = IOVDD = 1.8 V, unless otherwise noted.
ADS42JB46 ser_write_las900.gifFigure 1. Serial Register Write Timing Diagram
ADS42JB46 tim_reset_bas533.gif
NOTE: After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin.
Figure 2. Reset Timing Diagram
ADS42JB46 timing3_las900.gif
1. Overall latency = ADC latency + tD.
2. x = A for channel A and B for channel B.
Figure 3. ADC Latency
ADS42JB46 tim_sync_cgs_las900.gif
1. x = A for channel A and B for channel B.
Figure 4. SYNC~ Latency in CGS Phase (Two-Lane Mode)
ADS42JB46 tim_sync_ilas_las900.gif
1. x = A for channel A and B for channel B.
Figure 5. SYNC~ Latency in ILAS Phase (Two-Lane Mode)
ADS42JB46 timing1_las900.gifFigure 6. SYSREF Timing (Subclass 1)
ADS42JB46 timing2_las900.gifFigure 7. SYNC~ Timing (Subclass 2)

7.11 Typical Characteristics: ADS42JB46

Typical values are at TA = +25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted.
ADS42JB46 G003_SBAS621.pngFigure 8. FFT for 300-MHz Input Signal
ADS42JB46 G005_SBAS621.pngFigure 10. FFT for 170-MHz Input Signal
(2.5-VPP Full-Scale)
ADS42JB46 G007_SBAS621.pngFigure 12. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
ADS42JB46 G009_SBAS621.pngFigure 14. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
ADS42JB46 G011_SBAS621.pngFigure 16. Intermodulation Distortion vs
Input Amplitude (46 MHz and 50 MHz)
ADS42JB46 G013_SBAS621.pngFigure 18. Spurious-Free Dynamic Range vs
Input Frequency
ADS42JB46 G015_SBAS621.pngFigure 20. Spurious-Free Dynamic Range vs
Digital Gain
ADS42JB46 G017_SBAS621.pngFigure 22. Performance vs Input Amplitude
(70 MHz)
ADS42JB46 G019_SBAS621.pngFigure 24. Performance vs
Input Common-Mode Voltage (70 MHz)
ADS42JB46 G021_SBAS621.pngFigure 26. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
ADS42JB46 G023_SBAS621.pngFigure 28. Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature (170 Mhz)
ADS42JB46 G025_SBAS621.pngFigure 30. Spurious-Free Dynamic Range vs
DRVDD Supply and Temperature (170 MHz)
ADS42JB46 G027_SBAS621.pngFigure 32. Performance vs Clock Amplitude
(70 MHz)
ADS42JB46 G029_SBAS621.pngFigure 34. Performance vs Clock Duty Cycle
(70 MHz)
ADS42JB46 G031_SBAS621.pngFigure 36. Common-Mode Rejection Ratio FFT
ADS42JB46 G033_SBAS621.pngFigure 38. Power-Supply Rejection Ratio FFT for AVDD Supply
ADS42JB46 G035_SBAS621.pngFigure 40. Total Power vs Sampling Frequency
ADS42JB46 G004_SBAS621.pngFigure 9. FFT for 10-MHz Input Signal
(2.5-VPP Full-Scale)
ADS42JB46 G006_SBAS621.pngFigure 11. FFT for 300-MHz Input Signal
(2.5-VPP Full-Scale)
ADS42JB46 G008_SBAS621.pngFigure 13. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
ADS42JB46 G010_SBAS621.pngFigure 15. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
ADS42JB46 G012_SBAS621.pngFigure 17. Intermodulation Distortion vs
Input Amplitude (185 MHz and 190 MHz)
ADS42JB46 G014_SBAS621.pngFigure 19. Signal-to-Noise Ratio vs
Input Frequency
ADS42JB46 G016_SBAS621.pngFigure 21. Signal-to-Noise Ratio vs
Digital Gain
ADS42JB46 G018_SBAS621.pngFigure 23. Performance vs Input Amplitude
(170 MHz)
ADS42JB46 G020_SBAS621.pngFigure 25. Performance vs
Input Common-Mode Voltage (170 MHz)
ADS42JB46 G022_SBAS621.pngFigure 27. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
ADS42JB46 G024_SBAS621.pngFigure 29. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature (170 MHz)
ADS42JB46 G026_SBAS621.pngFigure 31. Signal-to-Noise Ratio vs
DRVDD Supply and Temperature (170 MHz)
ADS42JB46 G028_SBAS621.pngFigure 33. Performance vs Clock Amplitude
(170 MHz)
ADS42JB46 G030_SBAS621.pngFigure 35. Performance vs Clock Duty Cycle
(170 MHz)
ADS42JB46 G032_SBAS621.pngFigure 37. Common-Mode Rejection Ratio vs
Test Signal Frequency
ADS42JB46 G034_SLAS621.pngFigure 39. Power-Supply Rejection Ratio vs
Test Signal Frequency
ADS42JB46 G036_SBAS621.pngFigure 41. Analog Power vs Sampling Frequency

7.12 Typical Characteristics: Contour

Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, –1-dBFS differential input, 2-VPP full-scale, and 64k-point FFT, unless otherwise noted.

7.12.1 Spurious-Free Dynamic Range (SFDR)

ADS42JB46 G037_SBAS621.gifFigure 42. 0-dB Gain (SFDR)
ADS42JB46 G038_SBAS621.gifFigure 43. 6-dB Gain (SFDR)

7.12.2 Signal-to-Noise Ratio (SNR)

ADS42JB46 G039_SBAS621.gifFigure 44. 0-dB Gain
ADS42JB46 G040_SBAS621.gifFigure 45. 6-dB Gain