SBAS948B December   2018  – September 2025 ADS52J65 , ADS52J66

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Device and Documentation Support
    1. 4.1 Related Documentation
    2. 4.2 Receiving Notification of Documentation Updates
    3. 4.3 Support Resources
    4. 4.4 Trademarks
    5. 4.5 Electrostatic Discharge Caution
    6. 4.6 Glossary
  6. 5Revision History
  7. 6Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 16/14-Bit Resolution, 8/4-Channel ADC
  • Idle Signal-to-Noise Ratio (SNR):
    • 80dBFS for 16bit ADC
    • 79dBFS for 14bit ADC
  • Power dissipation at 125MSPS, 4CH per Lane:
    • 70mW/Ch for ADS52J65/66 (8CH ADC)
    • 82mW/Ch for ADS52J67/68 (4CH ADC)
  • Power dissipation at 62.5MSPS, 8CH per Lane:
    • 45mW/Ch for ADS52J65/66 (8CH ADC)
    • 65mW/Ch for ADS52J67/66 (4CH ADC)
  • Full-Scale Input: 2VPP
  • Full-Scale SNR at fIN = 10MHz:
    • 78dBFS for 16bit ADC
    • 77dBFS for 14bit ADC
  • Full-Scale SFDR: –85dBc at fin = 10MHz
  • Analog Input –3dB Bandwidth = 250MHz
  • Maximum Input Signal Frequency for 2VPP Input = 130MHz
  • Fast and Consistent Overload Recovery
  • Advanced Digital Features
    • Automatic DC Offset Correction
    • Digital Average
  • Digital I/Q Demodulator
    • Fractional Decimation Filter M = 1 to 63 With Increments of 0.25
    • Data Output Rate Reduction After Decimation
    • Power dissipation at 80MSPS and Decimation = 2
      • 64mW/Ch for ADS52J65/66 (8-CH ADC)
      • 91mW/Ch for ADS52J67/68 (4-CH ADC)
    • On-Chip RAM With 32 Preset Profiles
  • JESD204B Subclass 0, 1, and 2
    • 2, 4, or 8 Channels per JESD Lane
    • 10Gbps JESD Interface
    • Supports lane rate up to 12.8Gbps for short trace length (< 5 Inch)
  • 64-Pin Non-Magnetic 9 × 9mm Package