SBAS547D May   2013  – August 2015 ADS8881


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Companion Products
  6. Device Comparison
  7. Pin Configurations and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements: 3-Wire Operation
    7. 8.7 Timing Requirements: 4-Wire Operation
    8. 8.8 Timing Requirements: Daisy-Chain
    9. 8.9 Typical Characteristics
  9. Parametric Measurement Information
    1. 9.1 Equivalent Circuits
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Analog Input
      2. 10.3.2 Reference
      3. 10.3.3 Clock
      4. 10.3.4 ADC Transfer Function
    4. 10.4 Device Functional Modes
      1. 10.4.1 CS Mode
        1. 3-Wire CS Mode Without a Busy Indicator
        2. 3-Wire CS Mode With a Busy Indicator
        3. 4-Wire CS Mode Without a Busy Indicator
        4. 4-Wire CS Mode With a Busy Indicator
      2. 10.4.2 Daisy-Chain Mode
        1. Daisy-Chain Mode Without a Busy Indicator
        2. Daisy-Chain Mode With a Busy Indicator
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 ADC Reference Driver
      2. 11.1.2 ADC Input Driver
        1. Input Amplifier Selection
        2. Antialiasing Filter
    2. 11.2 Typical Applications
      1. 11.2.1 DAQ Circuit for a 1-µs, Full-Scale Step Response
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      2. 11.2.2 Low-Power DAQ Circuit for Excellent Dynamic Performance at 1 MSPS
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      3. 11.2.3 DAQ Circuit for Lowest Distortion and Noise Performance at 1 MSPS
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      4. 11.2.4 Ultralow-Power DAQ Circuit at 10 kSPS
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
  12. 12Power-Supply Recommendations
    1. 12.1 Power-Supply Decoupling
    2. 12.2 Power Saving
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Development Support
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Community Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Layout

13.1 Layout Guidelines

Figure 77 shows a board layout example for the device. Appropriate layout that interconnects accompanying capacitors and converters with low inductance is critical for achieving optimum performance. Thus, a PCB board with at least four layers is recommended to keep all critical components on the top layer and interconnected to a solid (low inductance) analog ground plane at the subsequent inner layer using 15-mil vias. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference input signals away from noise sources. As shown in Figure 77, the analog input and reference signals are routed on the left side of the board and the digital connections are routed on the right side of the device.

As a result of dynamic currents during conversion and data transfer, each supply pin (AVDD and DVDD) must have a decoupling capacitor to keep the supply voltage stable. To maximize decoupling capabilities, inductance between each supply capacitor and the supply pin of the converter is kept less than 5 nH by placing the capacitor within 0.2-inches from the pin and connecting it with 20-mil traces and a 15-mil grounding via, as shown in Figure 77. TI recommends using one 1-μF ceramic capacitor at each supply pin. Avoid placing vias between the supply pin and its decoupling capacitor.

Dynamic currents are also present at the REF pin during the conversion phase and very good decoupling is critical to achieve optimum performance. The inductance between the reference capacitor and the REF pin is kept less than 2 nH by placing the capacitor within 0.1-inches from the pin and connecting it with 20-mil traces and multiple 15-mil grounding vias, as shown in Figure 77. A single, 10-μF, X7R-grade, 0805-size, ceramic capacitor with at least a 10-V rating is recommended for good performance over the rated temperature range. Avoid using additional lower value capacitors because the interactions between multiple capacitors may affect the ADC performance at higher sampling rates. A small, 0.1-Ω to 0.47-Ω, 0603-size resistor placed in series with the reference capacitor (as shown in Figure 77) keeps the overall impedance low and constant, especially at very high frequencies.

The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.

13.2 Layout Example

ADS8881 ADS88xx_diff_LAYOUT.gif Figure 77. Recommended Layout