SBASAX3A May   2025  – September 2025 ADS9326 , ADS9327

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics 
    6. 6.6  Electrical Characteristics: AVDD = 5V
    7. 6.7  Electrical Characteristics: AVDD = 3.3V
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Reference
        1. 7.3.2.1 Internal Reference
          1. 7.3.2.1.1 Selectable Internal Reference with 5V AVDD
        2. 7.3.2.2 External Reference
        3. 7.3.2.3 External Reference With External Reference Buffer
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Data Interface
      5. 7.3.5 Programmable Data Averaging Filter
        1. 7.3.5.1 Simple Average
          1. 7.3.5.1.1 Simple Average with Noncontinuous CONVST
        2. 7.3.5.2 Moving Average
      6. 7.3.6 CRC on Output Data Interface
      7. 7.3.7 ADC Output Data Randomizer
      8. 7.3.8 Data Frame Width
      9. 7.3.9 Daisy-Chain Mode
        1. 7.3.9.1 Daisy-Clock Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Normal Operation
      3. 7.4.3 Low-Latency Mode
      4. 7.4.4 CS-CONVST Short Mode
      5. 7.4.5 Register Read Mode
      6. 7.4.6 Initialization Sequence
    5. 7.5 Programming
      1. 7.5.1 SPI Frame Length for Register Operations
      2. 7.5.2 Register Map Lock
      3. 7.5.3 Register Write
      4. 7.5.4 Register Read
  9. 8 Register Map: ADS9327
    1. 8.1 Register Bank 0
    2. 8.2 Register Bank 1
    3. 8.3 Register Bank 2
  10. 9 Register Map: ADS9326
    1. 9.1 Register Bank 0
    2. 9.2 Register Bank 1
    3. 9.3 Register Bank 2
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Analog 1VPP Sine-Cosine Encoder Interface
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
  • VAE|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.6 Initialization Sequence

As shown in Table 7-10 and Table 7-11, initialize ADS9326 and ADS9327 respectively with a sequence of register writes after device power-up or reset. The device registers are initialized with the default value after the initialization sequence is complete.

Table 7-10 ADS9326 Initialization Sequence
STEP NUMBER REGISTER DESCRIPTION
BANK ADDRESS VALUE[15:0]
1 0 0xFE 0xB38F Register map unlock sequence frame 1
2 0xFE 0xABCD Register map unlock sequence frame 2
3 0 0x01 0x0002 Software reset
4 Wait 1ms
5 0 0x01 0x0000 Clear software reset
6 0 0xFE 0xB38F Register map unlock sequence frame 1
7 0 0xFE 0xABCD Register map unlock sequence frame 2
8 0 0x02 0x0002 Select register bank 1
9 1 0x0C 0x1200 Select internal reference and INIT_0(0xC[12]) = 1
10 Wait 25ms
11 1 0x0C 0x0200 INIT_0(0xC[12]) = 0
12 0 0x03 0x000B Unlock register bank 2
13 0 0x02 0x0008 Select register bank 2
14 2 0x22 0x0080 INIT_2 = 1
15 0 0x02 0x0002 Select register bank 1
16 0 0xFE 0x1234 Register map lock sequence
Table 7-11 ADS9327 Initialization Sequence
STEP NUMBER REGISTER DESCRIPTION
BANK ADDRESS VALUE[15:0]
1 0 0xFE 0xB38F Register map unlock sequence frame 1
2 0 0xFE 0xABCD Register map unlock sequence frame 2
3 0 0x01 0x0002 Software reset
4 Wait 1ms
5 0 0x01 0x0000 Clear software reset
6 0 0xFE 0xB38F Register map unlock sequence frame 1
7 0 0xFE 0xABCD Register map unlock sequence frame 2
8 0 0x02 0x0002 Select register bank 1
9 1 0x0C 0x0200 Select internal reference.
10 0 0x03 0x000B Unlock register bank 2.
11 0 0x02 0x0008 Select register bank 2.
12 2 0x0F 0x4000 INIT_1 = 1
13 0 0x02 0x0002 Select register bank 1
14 0 0xFE 0x1234 Register map lock sequence