SBAS619A March   2014  – June 2017 AFE5401-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Digital Characteristics
    7. 6.7  Timing Requirements: Output Interface
    8. 6.8  Timing Requirements: RESET
    9. 6.9  Timing Requirements: Serial Interface Operation
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Timing Requirements: Across Output Serialization Modes
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Low-Noise Amplifier (LNA)
      2. 9.3.2 Programmable Gain Amplifier (PGA)
      3. 9.3.3 Antialiasing Filter
      4. 9.3.4 Analog-to-Digital Converter (ADC)
      5. 9.3.5 Digital Gain
      6. 9.3.6 Input Clock Divider
      7. 9.3.7 Data Output Serialization
      8. 9.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 9.3.8.1 Main Channels
        2. 9.3.8.2 Auxiliary Channel
    4. 9.4 Device Functional Modes
      1. 9.4.1 Equalizer Mode
      2. 9.4.2 Data Output Mode
        1. 9.4.2.1 Header
        2. 9.4.2.2 Test Pattern Mode
      3. 9.4.3 Parity
      4. 9.4.4 Standby, Power-Down Mode
      5. 9.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 9.4.5.1 Decimate-by-2 Mode
        2. 9.4.5.2 Decimate-by-4 Mode
      6. 9.4.6 Diagnostic Mode
      7. 9.4.7 Signal Chain Probe
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
      2. 9.5.2 Register Initialization
        1. 9.5.2.1 Register Write Mode
        2. 9.5.2.2 Register Read Mode
      3. 9.5.3 CMOS Output Interface
        1. 9.5.3.1 Synchronization and Triggering
    6. 9.6 Register Maps
      1. 9.6.1 Functional Register Map
      2. 9.6.2 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Power Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The AFE5401-Q1 is a quad-channel, analog front-end (AFE), targeting applications where the level of integration is critical. Each channel comprises a complete base-band signal chain with:

  • A low-noise amplifier (LNA),
  • A programmable equalizer (EQ),
  • A programmable gain amplifier (PGA), and
  • An antialias filter (AAF)
  • A high-speed, 12-bit, analog-to-digital converter (ADC) that samples at 25 MSPS per channel.

Having four integrated signal chain channels enables the device to be used in different end-use systems such as:

  • Automotive radar (where a down-converted base-band signal from an RF front-end can be applied to the inputs of the AFE)
  • Applications where up to 12-MHz voltage signal is available from a transducer

10.2 Typical Application

As Figure 122 illustrates, the device also consists of four auxiliary channels, where the analog signal chain (LNA, PGA) is bypassed and the analog inputs can be directly digitized. This configuration is very useful in the system to digitize monitoring signals (such as battery voltages and temperature sensor outputs).

As the Design Requirements section describes, the device can accept a variety of input clock signals (such as differential sine-wave, LVPECL, or LVDS). The can also functions seamlessly with a single-ended LVCMOS (1.8 V) clock input.

The device is designed to have a simple CMOS output data interface. Used with the TRIG and DSYNCx signals, the device can be interfaced to standard video ports of DSPs and other field-programmable gate array (FPGA) and micro-controller based receivers.

AFE5401-Q1 Applct_Sctn_BD_BAS619.gif Figure 122. Typical Application Diagram

10.2.1 Design Requirements

The device can operate with either single-ended (CMOS) or differential input clocks (such as sine wave, LVPECL, and LVDS). Operating with a low-jitter differential clock is recommended for good SNR performance. In differential mode, the clock inputs are internally biased to the optimum common-mode voltage (approximately 0.95 V). While driving with an external LVPECL or LVDS driver, TI recommends ac-coupling the clock signals because the clock pins are internally biased to the common-mode voltage.

10.2.2 Detailed Design Procedure

For the LVDS input clock, RTERM = 100 Ω is recommended. For the LVPECL clock input, RTERM must be determined based on the LVPECL driver recommendations. To operate using a single-ended clock, connect a CMOS clock source to CLKINP and tie CLKINM to GND. The device automatically detects the presence of a single-ended clock without requiring any configuration and disables internal biasing. Typical clock termination schemes are illustrated in Figure 125, Figure 126, Figure 127, and Figure 128. Typical characteristic plots across input clock amplitude and duty cycle are shown in Application Curves.

Figure 123 and Figure 124 illustrate the equivalent circuits of the clock input pins for Differential and Single-Ended input clock respectively.

AFE5401-Q1 Clk_Inpt_eq_Crct_Diffrntl_BAS619.gif Figure 123. Clock Input Equivalent Circuit (Differential Mode)
AFE5401-Q1 Clk_Inpt_eq_Crct_Sngl_end_BAS619.gif Figure 124. Clock Input Equivalent Circuit (Single-Ended Mode)
AFE5401-Q1 Diffrntl_Sin_wv_Clck_BAS619.gif Figure 125. Differential Sine-Wave Clock
Driving Circuit
AFE5401-Q1 Diffrntl_LVDS_Clck_BAS619.gif Figure 127. Differential LVDS Clock Driving Circuit
AFE5401-Q1 Diffrntl_LVPCL_Clck_BAS619.gif Figure 126. Differential LVPECL Clock
Driving Circuit
AFE5401-Q1 Sngl_End_Clck_Drvn_BAS619.gif Figure 128. Single-Ended Clock Driving Circuit

10.2.3 Application Curves

AFE5401-Q1 C011_BAS619.png Figure 129. Signal-to-Noise Ratio vs Input Clock Amplitude (PGA Gain = 0 dB)
AFE5401-Q1 C013_BAS619.png Figure 130. Signal-to-Noise Ratio vs Input Clock Duty Cycle (PGA Gain = 0 dB)