SBAS619A March   2014  – June 2017 AFE5401-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Digital Characteristics
    7. 6.7  Timing Requirements: Output Interface
    8. 6.8  Timing Requirements: RESET
    9. 6.9  Timing Requirements: Serial Interface Operation
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Timing Requirements: Across Output Serialization Modes
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Low-Noise Amplifier (LNA)
      2. 9.3.2 Programmable Gain Amplifier (PGA)
      3. 9.3.3 Antialiasing Filter
      4. 9.3.4 Analog-to-Digital Converter (ADC)
      5. 9.3.5 Digital Gain
      6. 9.3.6 Input Clock Divider
      7. 9.3.7 Data Output Serialization
      8. 9.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 9.3.8.1 Main Channels
        2. 9.3.8.2 Auxiliary Channel
    4. 9.4 Device Functional Modes
      1. 9.4.1 Equalizer Mode
      2. 9.4.2 Data Output Mode
        1. 9.4.2.1 Header
        2. 9.4.2.2 Test Pattern Mode
      3. 9.4.3 Parity
      4. 9.4.4 Standby, Power-Down Mode
      5. 9.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 9.4.5.1 Decimate-by-2 Mode
        2. 9.4.5.2 Decimate-by-4 Mode
      6. 9.4.6 Diagnostic Mode
      7. 9.4.7 Signal Chain Probe
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
      2. 9.5.2 Register Initialization
        1. 9.5.2.1 Register Write Mode
        2. 9.5.2.2 Register Read Mode
      3. 9.5.3 CMOS Output Interface
        1. 9.5.3.1 Synchronization and Triggering
    6. 9.6 Register Maps
      1. 9.6.1 Functional Register Map
      2. 9.6.2 Register Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Power Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGC Package
VQFN-64
Top View
AFE5401-Q1 PO_nw_bas619.gif

Pin Functions

PIN DESCRIPTION
NAME NO
D[11:0] 35-46 CMOS outputs for channels 1 to 4
D_GPO[1:0] 47, 48 General-purpose CMOS output
AVDD3 18 3.3-V analog supply voltage
AVDD18 19, 24, 62 1.8-V analog supply voltage
AVSS 20, 23, 61, 63 Analog ground
CLKINM 22 Negative differential clock input pin. A single-ended clock is also supported.
CLKINP 21 Positive differential clock input pin. A single-ended clock is also supported.
DCLK 34 CMOS output clock
DRVDD 32, 33, 50 CMOS output driver supply
DRVSS 31, 49 CMOS output driver ground
DSYNC1 26 Data synchronization clock 1
DSYNC2 27 Data synchronization clock 2
DVDD18 28, 30, 51 1.8-V digital supply voltage
DVSS 29, 52 Digital ground
IN1M 4 Negative differential analog input pin for channel 1
IN1P 3 Positive differential analog input pin for channel 1
IN1M_AUX 2 Negative differential auxiliary analog input pin for channel 1
IN1P_AUX 1 Positive differential auxiliary analog input pin for channel 1
IN2M 8 Negative differential analog input pin for channel 2
IN2P 7 Positive differential analog input pin for channel 2
IN2M_AUX 6 Negative differential auxiliary analog input pin for channel 2
IN2P_AUX 5 Positive differential auxiliary analog input pin for channel 2
IN3M 12 Negative differential analog input pin for channel 3
IN3P 11 Positive differential analog input pin for channel 3
IN3M_AUX 10 Negative differential auxiliary analog input pin for channel 3
IN3P_AUX 9 Positive differential auxiliary analog input pin for channel 3
IN4M 16 Negative differential analog input pin for channel 4
IN4P 15 Positive differential analog input pin for channel 4
IN4P_AUX 13 Positive differential auxiliary analog input pin for channel 4
IN4M_AUX 14 Negative differential auxiliary analog input pin for channel 4
NC 58, 60 Do not connect
RESET 57 Hardware reset pin (active high). This pin has an internal 150-kΩ pull-down resistor.
SCLK 56 Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
SDATA 55 Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
SDOUT 53 Serial interface data readout
SEN 54 Serial interface enable. This pin has an internal 150-kΩ pull-up resistor.
STBY 59 Standby control input. This pin has an internal 150-kΩ pull-down resistor.
TRIG 25 Trigger for DSYNC1 and DSYNC2. This pin has an internal 150-kΩ pull-down resistor.
VCM 17, 64 Output pins for common-mode bias voltage of the auxiliary input signals
Thermal pad Pad Located on bottom of package, internally connected to AVSS. Connect to ground plane on the board.