SPRSP81D October   2023  – May 2025 AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Device Identification
    2. 4.2 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 ZCZ_C Pin Diagram
      2. 5.1.2 ZCZ_S Pin Diagram
      3. 5.1.3 ZCZ_F Pin Diagram
    2. 5.2 Pin Attributes
      1.      15
      2.      16
    3. 5.3 Signal Descriptions
      1.      18
      2. 5.3.1  ADC
        1.       20
        2.       21
        3.       22
        4.       23
        5.       24
        6. 5.3.1.1 ADC-CMPSS Signal Connections
      3. 5.3.2  ADC Resolver
        1.       27
        2.       28
        3.       29
      4. 5.3.3  ADC_CAL
        1.       31
      5. 5.3.4  ADC VREF
        1.       33
      6. 5.3.5  CPSW
        1.       35
        2.       36
        3.       37
        4.       38
        5.       39
        6.       40
        7.       41
      7. 5.3.6  CPTS
        1.       43
      8. 5.3.7  DAC
        1.       45
      9. 5.3.8  EPWM
        1.       47
        2.       48
        3.       49
        4.       50
        5.       51
        6.       52
        7.       53
        8.       54
        9.       55
        10.       56
        11.       57
        12.       58
        13.       59
        14.       60
        15.       61
        16.       62
        17.       63
        18.       64
        19.       65
        20.       66
        21.       67
        22.       68
        23.       69
        24.       70
        25.       71
        26.       72
        27.       73
        28.       74
        29.       75
        30.       76
        31.       77
        32.       78
      10. 5.3.9  EQEP
        1.       80
        2.       81
        3.       82
      11. 5.3.10 FSI
        1.       84
        2.       85
        3.       86
        4.       87
        5.       88
        6.       89
        7.       90
        8.       91
      12. 5.3.11 GPIO
        1.       93
      13. 5.3.12 I2C
        1.       95
        2.       96
        3.       97
        4.       98
        5.       99
      14. 5.3.13 LIN
        1.       101
        2.       102
        3.       103
        4.       104
        5.       105
      15. 5.3.14 MCAN
        1.       107
        2.       108
        3.       109
        4.       110
        5.       111
        6.       112
        7.       113
        8.       114
      16. 5.3.15 SPI (MCSPI)
        1.       116
        2.       117
        3.       118
        4.       119
        5.       120
        6.       121
        7.       122
        8.       123
      17. 5.3.16 MMC
        1.       125
      18. 5.3.17 OSPI (Shared)
        1.       127
      19. 5.3.18 Power Supply
        1.       129
      20. 5.3.19 PRU-ICSS
        1.       131
        2.       132
        3.       133
        4.       134
        5.       135
      21. 5.3.20 SDFM
        1.       137
        2.       138
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1.        141
        2. 5.3.21.2 Clocking
          1.        143
          2.        144
          3.        145
        3. 5.3.21.3 Emulation and Debug
          1.        147
          2.        148
        4. 5.3.21.4 SYSTEM
          1.        150
        5. 5.3.21.5 VMON
          1.        152
        6. 5.3.21.6 Reserved and No Connect
          1.        154
          2.        155
      23. 5.3.22 UART
        1.       157
        2.       158
        3.       159
        4.       160
        5.       161
        6.       162
      24. 5.3.23 XBAR
        1.       164
        2.       165
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Electrostatic Discharge (ESD) Extended Automotive Ratings
    3. 6.3  Electrostatic Discharge (ESD) Industrial Ratings
    4. 6.4  Power-On Hours (POH) Summary
      1. 6.4.1 Automotive Temperature Profiles
        1. 6.4.1.1 Automotive Temperature Profile
        2. 6.4.1.2 Automotive Temperature Profile ZCZ-F
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
      1. 6.6.1 ZCZ_F Package Flash Retention Specifications
    7. 6.7  Power Consumption Summary
      1. 6.7.1 Power Consumption - Maximum
      2. 6.7.2 Power Consumption - Typical
      3. 6.7.3 Power Consumption - Traction Inverter
    8. 6.8  Electrical Characteristics
      1. 6.8.1 Digital and Analog IO Electrical Characteristics
      2. 6.8.2 Analog to Digital Converter Characteristics
        1. 6.8.2.1 Analog-to-Digital Converter (ADC)
        2. 6.8.2.2 Resolver Analog-to-Digital Converter (ADC_R)
        3. 6.8.2.3 ADC Input Model
      3. 6.8.3 Comparator Subsystem A (CMPSSA)
      4. 6.8.4 Comparator Subsystem B (CMPSSB)
      5. 6.8.5 Digital-to-Analog Converter (DAC)
      6. 6.8.6 Power Management Unit (PMU)
      7. 6.8.7 Safety Comparators
      8. 6.8.8 Safety System
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 VPP Specifications
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Package Thermal Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Sequencing
        1. 6.11.2.1 Power-On and Reset Sequencing
          1. 6.11.2.1.1 Power Reset Sequence Description
        2. 6.11.2.2 Power-Down Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 System Timing Conditions
        2. 6.11.3.2 Reset Timing
          1. 6.11.3.2.1 PORz Timing Requirements
          2.        211
          3. 6.11.3.2.2 WARMRSTn Switching Characteristics
          4.        213
          5. 6.11.3.2.3 WARMRSTn Timing Requirements
          6.        215
        3. 6.11.3.3 Safety Signal Timing
          1. 6.11.3.3.1 SAFETY_ERRORn Switching Characteristics
          2.        218
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 Crystal Oscillator (XTAL) Parameters
          2. 6.11.4.1.2 External Clock Characteristics
      5. 6.11.5 Peripherals
        1. 6.11.5.1  2-port Gigabit Ethernet MAC (CPSW)
          1. 6.11.5.1.1 CPSW MDIO Timing
            1. 6.11.5.1.1.1 CPSW MDIO Timing Conditions
            2. 6.11.5.1.1.2 CPSW MDIO Timing Requirements
            3. 6.11.5.1.1.3 CPSW MDIO Switching Characteristics
            4.         229
          2. 6.11.5.1.2 CPSW RGMII Timing
            1. 6.11.5.1.2.1 CPSW RGMII Timing Conditions
            2. 6.11.5.1.2.2 CPSW RGMII[x]_RCLK Timing Requirements - RGMII Mode
            3. 6.11.5.1.2.3 CPSW RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements
            4.         234
            5. 6.11.5.1.2.4 CPSW RGMII[x]_TCLK Switching Characteristics - RGMII Mode
            6. 6.11.5.1.2.5 CPSW RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
            7.         237
          3. 6.11.5.1.3 CPSW RMII Timing
            1. 6.11.5.1.3.1 CPSW RMII Timing Conditions
            2. 6.11.5.1.3.2 CPSW RMII[x]_REFCLK Timing Requirements - RMII Mode
            3.         241
            4. 6.11.5.1.3.3 CPSW RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
            5.         243
            6. 6.11.5.1.3.4 CPSW RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
            7.         245
        2. 6.11.5.2  Enhanced Capture (eCAP)
          1. 6.11.5.2.1 ECAP Timing Conditions
          2. 6.11.5.2.2 ECAP Timing Requirements
          3.        249
          4. 6.11.5.2.3 ECAP Switching Characteristics
          5.        251
        3. 6.11.5.3  Enhanced Pulse Width Modulation (ePWM)
          1. 6.11.5.3.1 EPWM Timing Conditions
          2. 6.11.5.3.2 EPWM Timing Requirements
          3.        255
          4. 6.11.5.3.3 EPWM Switching Characteristics
          5.        257
          6. 6.11.5.3.4 EPWM Characteristics
        4. 6.11.5.4  Enhanced Quadrature Encoder Pulse (eQEP)
          1. 6.11.5.4.1 EQEP Timing Conditions
          2. 6.11.5.4.2 EQEP Timing Requirements
          3.        262
          4. 6.11.5.4.3 EQEP Switching Characteristics
        5. 6.11.5.5  Fast Serial Interface (FSI)
          1. 6.11.5.5.1 FSI Timing Conditions
          2. 6.11.5.5.2 FSIRX Timing Requirements
          3.        267
          4. 6.11.5.5.3 FSIRX Switching Characteristics
          5. 6.11.5.5.4 FSITX Switching Characteristics
          6.        270
          7. 6.11.5.5.5 FSITX SPI Signaling Mode Switching Characteristics
          8.        272
        6. 6.11.5.6  General Purpose Input/Output (GPIO)
          1. 6.11.5.6.1 GPIO Timing Conditions
          2. 6.11.5.6.2 GPIO Timing Requirements
          3. 6.11.5.6.3 GPIO Switching Characteristics
        7. 6.11.5.7  Inter-Integrated Circuit (I2C)
          1. 6.11.5.7.1 I2C
        8. 6.11.5.8  Local Interconnect Network (LIN)
          1. 6.11.5.8.1 LIN Timing Conditions
          2. 6.11.5.8.2 LIN Timing Requirements
          3. 6.11.5.8.3 LIN Switching Characteristics
        9. 6.11.5.9  Modular Controller Area Network (MCAN)
          1. 6.11.5.9.1 MCAN Timing Conditions
          2. 6.11.5.9.2 MCAN Switching Characteristics
        10. 6.11.5.10 Serial Peripheral Interface (SPI)
          1. 6.11.5.10.1 SPI Timing Conditions
          2. 6.11.5.10.2 SPI Controller Mode Timing Requirements
          3.        289
          4. 6.11.5.10.3 SPI Controller Mode Switching Characteristics (Clock Phase = 0)
          5.        291
          6. 6.11.5.10.4 SPI Peripheral Mode Timing Requirements
          7.        293
          8. 6.11.5.10.5 SPI Peripheral Mode Switching Characteristics
          9.        295
        11. 6.11.5.11 Multi-Media Card/Secure Digital (MMCSD)
          1. 6.11.5.11.1 MMC Timing Conditions
          2. 6.11.5.11.2 MMC Timing Requirements - SD Card Default Speed Mode
          3.        299
          4. 6.11.5.11.3 MMC Switching Characteristics - SD Card Default Speed Mode
          5.        301
          6. 6.11.5.11.4 MMC Timing Requirements - SD Card High Speed Mode
          7.        303
          8. 6.11.5.11.5 MMC Switching Characteristics - SD Card High Speed Mode
          9.        305
        12. 6.11.5.12 Octal Serial Peripheral Interface (OSPI)
          1. 6.11.5.12.1 OSPI Timing Conditions
          2. 6.11.5.12.2 OSPI PHY Mode
            1. 6.11.5.12.2.1 OSPI0 With PHY Data Training
              1. 6.11.5.12.2.1.1 OSPI DLL Delay Mapping for PHY Data Training
              2. 6.11.5.12.2.1.2 OSPI Timing Requirements - PHY Data Training
              3.          312
              4. 6.11.5.12.2.1.3 OSPI Switching Characteristics - PHY Data Training
              5.          314
            2. 6.11.5.12.2.2 OSPI0 Without Data Training
              1. 6.11.5.12.2.2.1 OSPI0 PHY SDR Timing
                1. 6.11.5.12.2.2.1.1 OSPI DLL Delay Mapping for PHY SDR Timing Modes
                2. 6.11.5.12.2.2.1.2 OSPI Timing Requirements - PHY SDR Mode
                3.           319
                4. 6.11.5.12.2.2.1.3 OSPI Switching Characteristics - PHY SDR Mode
                5.           321
              2. 6.11.5.12.2.2.2 OSPI0 PHY DDR Timing
                1. 6.11.5.12.2.2.2.1 OSPI DLL Delay Mapping for PHY DDR Timing Modes
                2. 6.11.5.12.2.2.2.2 OSPI Timing Requirements - PHY DDR Mode
                3.           325
                4. 6.11.5.12.2.2.2.3 OSPI Switching Characteristics - PHY DDR Mode
                5.           327
          3. 6.11.5.12.3 OSPI Tap Mode
            1. 6.11.5.12.3.1 OSPI0 Tap SDR Timing
              1. 6.11.5.12.3.1.1 OSPI Timing Requirements - Tap SDR Mode
              2.          331
              3. 6.11.5.12.3.1.2 OSPI Switching Characteristics - Tap SDR Mode
              4.          333
            2. 6.11.5.12.3.2 OSPI0 Tap DDR Timing
              1. 6.11.5.12.3.2.1 OSPI Timing Requirements - Tap DDR Mode
              2.          336
              3. 6.11.5.12.3.2.2 OSPI Switching Characteristics - Tap DDR Mode
              4.          338
        13. 6.11.5.13 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
          1. 6.11.5.13.1 PRU-ICSS Programmable Real-Time Unit (PRU)
            1. 6.11.5.13.1.1 PRU-ICSS PRU Timing Conditions
            2. 6.11.5.13.1.2 PRU-ICSS PRU Switching Characteristics - Direct Output Mode
            3.         343
            4. 6.11.5.13.1.3 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            5.         345
            6. 6.11.5.13.1.4 PRU-ICSS PRU Timing Requirements - Shift In Mode
            7.         347
            8. 6.11.5.13.1.5 PRU-ICSS PRU Switching Characteristics - Shift Out Mode
            9.         349
          2. 6.11.5.13.2 PRU-ICSS PRU Sigma Delta and Peripheral Interface
            1. 6.11.5.13.2.1 PRU-ICSS PRU Sigma Delta and Peripheral Interface Timing Conditions
            2. 6.11.5.13.2.2 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            3.         353
            4. 6.11.5.13.2.3 PRU-ICSS PRU Timing Requirements - Peripheral Interface Mode
            5.         355
            6. 6.11.5.13.2.4 PRU-ICSS PRU Switching Characteristics - Peripheral Interface Mode
            7.         357
          3. 6.11.5.13.3 PRU-ICSS Pulse Width Modulation (PWM)
            1. 6.11.5.13.3.1 PRU-ICSS PWM Timing Conditions
            2. 6.11.5.13.3.2 PRU-ICSS PWM Switching Characteristics
            3.         361
          4. 6.11.5.13.4 PRU-ICSS Industrial Ethernet Peripheral (IEP)
            1. 6.11.5.13.4.1 PRU-ICSS IEP Timing Conditions
            2. 6.11.5.13.4.2 PRU-ICSS IEP Timing Requirements - Input Validated with SYNCx
            3.         365
            4. 6.11.5.13.4.3 PRU-ICSS IEP Timing Requirements - Digital IOs
            5.         367
            6. 6.11.5.13.4.4 PRU-ICSS IEP Timing Requirements - LATCHx_IN
            7.         369
          5. 6.11.5.13.5 PRU-ICSS Universal Asynchronous Receiver Transmitter (UART)
            1. 6.11.5.13.5.1 PRU-ICSS UART Timing Conditions
            2. 6.11.5.13.5.2 PRU-ICSS UART Timing Requirements
            3. 6.11.5.13.5.3 PRU-ICSS UART Switching Characteristics
            4.         374
          6. 6.11.5.13.6 PRU-ICSS Enhanced Capture Peripheral (ECAP)
            1. 6.11.5.13.6.1 PRU-ICSS ECAP Timing Conditions
            2. 6.11.5.13.6.2 PRU-ICSS ECAP Timing Requirements
            3.         378
            4. 6.11.5.13.6.3 PRU-ICSS ECAP Switching Characteristics
            5.         380
          7. 6.11.5.13.7 PRU-ICSS MDIO and MII
            1. 6.11.5.13.7.1 PRU-ICSS MDIO Timing
              1. 6.11.5.13.7.1.1 PRU-ICSS MDIO Timing Conditions
              2. 6.11.5.13.7.1.2 PRU-ICSS MDIO Timing Requirements
              3. 6.11.5.13.7.1.3 PRU-ICSS MDIO Switching Characteristics
              4.          386
            2. 6.11.5.13.7.2 PRU-ICSS MII Timing
              1. 6.11.5.13.7.2.1 PRU-ICSS MII Timing Conditions
              2. 6.11.5.13.7.2.2 PRU-ICSS MII Timing Requirements - MII[x]_RX_CLK
              3.          390
              4. 6.11.5.13.7.2.3 PRU-ICSS MII Timing Requirements - MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER
              5.          392
              6. 6.11.5.13.7.2.4 PRU-ICSS MII Switching Characteristics - MII[x]_TX_CLK
              7.          394
              8. 6.11.5.13.7.2.5 PRU-ICSS MII Switching Characteristics - MII[x]_TXD[3:0] and MII[x]_TXEN
              9.          396
        14. 6.11.5.14 Sigma Delta Filter Module (SDFM)
          1. 6.11.5.14.1 SDFM Timing Conditions
          2. 6.11.5.14.2 SDFM Switching Characteristics
        15. 6.11.5.15 Universal Asynchronous Receiver/Transmitter (UART)
          1. 6.11.5.15.1 UART Timing Conditions
          2. 6.11.5.15.2 UART Timing Requirements
          3. 6.11.5.15.3 UART Switching Characteristics
          4.        404
      6. 6.11.6 Emulation and Debug
        1. 6.11.6.1 JTAG
          1. 6.11.6.1.1 JTAG Timing Conditions
          2. 6.11.6.1.2 JTAG Timing Requirements
          3. 6.11.6.1.3 JTAG Switching Characteristics
          4.        410
        2. 6.11.6.2 Trace
          1. 6.11.6.2.1 Debug Trace Timing Conditions
          2. 6.11.6.2.2 Debug Trace Switching Characteristics
          3.        414
    12. 6.12 Decoupling Capacitor Requirements
      1. 6.12.1 Decoupling Capacitor Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 External Oscillator
      2. 8.1.2 JTAG, EMU, and TRACE
      3. 8.1.3 OSPI Connections for Flash-in-Package (ZCZ_F)
      4. 8.1.4 UART Implementation
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Device Comparison

Table 6-4 shows a comparison between devices, highlighting the differences.

Table 4-1 Device Comparison
FEATURES REFERENCE
NAME		 AM263P4
AM263P4-Q1		 AM263P2
AM263P2-Q1
JTAG User ID
DEVICE_ID[31:13](1)
(Base Part Number)		 D: 0x30884 0x30844
E: 0x30885 0x30845
K: 0x3088B 0x3084B
L: 0x3088C 0x3084C
M: 0x3088D 0x3084D
N: 0x3088E -
PROCESSORS AND ACCELERATORS
Speed Grade See Section 6.6, Operating Performance Points
Arm® Cortex-R5F R5FSS 4 (2× Dual Core w/ Lockstep) 2 (1× Dual Core w/ Lockstep)
Trigonometric Math Unit TMU Yes
Hardware Security Module HSM Yes
Crypto Accelerators Security Yes
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) OCSRAM See Section 6.6, Operating Performance Points
R5F Tightly Coupled Memory (TCM) TCM Up to 512KB(10)
PERIPHERALS
Modular Controller Area Network with Full CAN-FD MCAN 8
General-Purpose I/O GPIO Up to 139
Serial Peripheral Interface SPI 8
Universal Asynchronous Receiver and Transmitter UART 6
Local Interconnect Network LIN 5
Inter-Integrated Circuit Interface I2C 4
Analog-to-Digital Converter ADC 3(2) or 5(3) 3(2) or 5(3)
Resolver (ADC12B3M)(4) RDC 0(8) or 2(9) 0(8) or 2(9)
ADC 0(8) or 2(9) 0(8) or 2(9)
Comparator Modules CMPSS 12(2) or 20(3) 12(2) or 20(3)
Digital-to-Analog Converter DAC 1
Programmable Real-Time Unit Subsystem(5) PRU-ICSS 0 or 1
Industrial Communication Subsystem Support(6) PRU-ICSS Optional
Gigabit Ethernet Interface CPSW Yes (2(8) or 1(9))
Multi-Media Card/Secure Digital Interface MMCSD 1
Enhanced High-Resolution Pulse-Width Modulator Module EHRPWM 16(2) or 32(3) 16(2) or 32(3)
Enhanced Capture Module ECAP 8(2) or 16(3) 8(2) or 16(3)
Enhanced Quadrature Encoder Pulse Module EQEP 2(2) or 3(3) 2(2) or 3(3)
Sigma Delta Filter Module SDFM 1(2) or 2(3) 1(2) or 2(3)
Fast Serial Interface FSI 4x FSI_RX + 4x FSI_TX
Octal SPI Flash Interface OSPI 1 or 0(11)

Flash-in-Package(ZCZ) Variant available

 ZCZ_F Yes No
Flash-in-Package density - 64Mb or 8MB -
Miscellaneous
Junction Temperature Extended Industrial: –40°C to 125°C
Extended Automotive: –40°C to 150°C(12)
Automotive Qualification AEC-Q100(7) Option
(1) Values listed here for DEVICE_ID are bits [31:13] of the TOP_CTRL.EFUSE_JTAG_USERCODE_ID register. For full JTAG ID's please refer to the Device Part Number Identifier table.
(2) Standard Analog configuration contains 3x ADC, 16x EHRPWM, 8x eCAP, 2x EQEP, 1x SDFM, 12x CMPSS
(3) Enhanced Analog configuration contains 5x ADC, 32x EHRPWM, 16x eCAP, 3x EQEP, 2x SDFM, 20x CMPSS
(4) The 2x Resolver ADC12B3M modules can be used as either Resolver ADCs or general-purpose ADCs
(5) Programmable Real-Time Unit Subsystem is available when selecting an orderable part number that includes a feature code of D, E, F, K, L, M, or N. Refer to the Nomenclature Description table for definition of feature codes.
(6) Industrial Communication Subsystem Support is available when selecting an orderable part number that includes a feature code of D, E, F, K, L, M, or N. Refer to the Nomenclature Description table for definition of feature codes.
(7) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the Nomenclature Description table.
(8) Applies to devices in the ZCZ-C Package only and have a Special Features code of C. Refer to the Nomenclature Description table for definition of Special Features codes.
(9) Applies to devices in the ZCZ-S Package and the ZCZ-F Package that have a Special Features code of F or S. Refer to the Nomenclature Description table for definition of Special Features codes.
(10) Each R5FSS cluster supports 256KB of Tightly-Coupled Memory (TCM). When configured as Single-Core or Lockstep operating mode, individual cores can utilize the entire 256KB of TCM memory, while in Dual-Core mode, each core may only utilize its designated half (128KB TCM).
(11) The Flash-in-Package variant connects the OSPI interface to an OSPI Flash die included in the package, disabling the external OSPI interface for application use. The flash device in the Flash-in-Package(ZCZ_F) variant does not support RWW(Read While Write) while performing XIP(eXecute-In-Place) operations.
(12) The Flash-in-Package variant is limited by the OSPI Flash device in the package to 125°C.