This section provides the timing specification for the DDR3 and DDR3L interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR3 or DDR3L memory system without the need for a complex timing closure process. For more information regarding the guidelines, see Understanding TI’s PCB Routing Rule-Based DDR Timing Specification. This application report provides generic guidelines and approach. All the specifications provided in the data manual take precedence over the generic guidelines and must be adhered to for a reliable DDR3 or DDR3L interface operation.
All references to DDR3 in this section apply to DDR3 and DDR3L devices, unless otherwise noted.