SPRS851E June   2014  – January 2019 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. Table 4-1 ZDN Ball Map [Section Top Left - Top View]
      2. Table 4-2 ZDN Ball Map [Section Top Middle - Top View]
      3. Table 4-3 ZDN Ball Map [Section Top Right - Top View]
      4. Table 4-4 ZDN Ball Map [Section Middle Left - Top View]
      5. Table 4-5 ZDN Ball Map [Section Middle Middle - Top View]
      6. Table 4-6 ZDN Ball Map [Section Middle Right - Top View]
      7. Table 4-7 ZDN Ball Map [Section Bottom Left - Top View]
      8. Table 4-8 ZDN Ball Map [Section Bottom Middle - Top View]
      9. Table 4-9 ZDN Ball Map [Section Bottom Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC Interfaces
      2. 4.3.2  CAN Interfaces
      3. 4.3.3  Camera (VPFE) Interfaces
      4. 4.3.4  Debug Subsystem Interface
      5. 4.3.5  Display Subsystem (DSS) Interface
      6. 4.3.6  Ethernet (GEMAC_CPSW) Interfaces
      7. 4.3.7  External Memory Interfaces
      8. 4.3.8  General Purpose IOs
      9. 4.3.9  HDQ Interface
      10. 4.3.10 I2C Interfaces
      11. 4.3.11 McASP Interfaces
      12. 4.3.12 Miscellaneous
      13. 4.3.13 PRU-ICSS0 Interface
      14. 4.3.14 PRU-ICSS1 Interface
      15. 4.3.15 QSPI Interface
      16. 4.3.16 RTC Subsystem Interface
      17. 4.3.17 Removable Media Interfaces
      18. 4.3.18 SPI Interfaces
      19. 4.3.19 Timer Interfaces
      20. 4.3.20 UART Interfaces
      21. 4.3.21 USB Interfaces
      22. 4.3.22 eCAP Interfaces
      23. 4.3.23 eHRPWM Interfaces
      24. 4.3.24 eQEP Interfaces
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  ADC0: Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters
    9. 5.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-6 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.9.1     Hardware Requirements
      3. 5.9.2     Programming Sequence
      4. 5.9.3     Impact to Your Hardware Warranty
    10. 5.10 Thermal Resistance Characteristics
      1. Table 5-7 Thermal Resistance Characteristics (NFBGA Package) [ZDN]
    11. 5.11 External Capacitors
      1. 5.11.1 Voltage Decoupling Capacitors
        1. 5.11.1.1 Core Voltage Decoupling Capacitors
        2. 5.11.1.2 IO and Analog Voltage Decoupling Capacitors
      2. 5.11.2 Output Capacitors
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. 5.12.1.1 Power Supply Slew Rate Requirement
        2. 5.12.1.2 Power-Up Sequencing
        3. 5.12.1.3 Power-Down Sequencing
      2. 5.12.2  Clock
        1. 5.12.2.1 PLLs
          1. 5.12.2.1.1 Digital Phase-Locked Loop Power Supply Requirements
        2. 5.12.2.2 Input Clock Specifications
        3. 5.12.2.3 Input Clock Requirements
          1. 5.12.2.3.1 OSC0 Internal Oscillator Clock Source
            1. Table 5-12 OSC0 Crystal Circuit Requirements
            2. Table 5-13 OSC0 Crystal Circuit Characteristics
          2. 5.12.2.3.2 OSC0 LVCMOS Digital Clock Source
          3. 5.12.2.3.3 OSC1 Internal Oscillator Clock Source
            1. Table 5-15 OSC1 Crystal Circuit Requirements
            2. Table 5-16 OSC1 Crystal Circuit Characteristics
          4. 5.12.2.3.4 OSC1 LVCMOS Digital Clock Source
          5. 5.12.2.3.5 OSC1 Not Used
        4. 5.12.2.4 Output Clock Specifications
        5. 5.12.2.5 Output Clock Characteristics
          1. 5.12.2.5.1 CLKOUT1
          2. 5.12.2.5.2 CLKOUT2
      3. 5.12.3  Timing Parameters and Board Routing Analysis
      4. 5.12.4  Recommended Clock and Control Signal Transition Behavior
      5. 5.12.5  Controller Area Network (CAN)
        1. 5.12.5.1 DCAN Electrical Data and Timing
          1. Table 5-18 Timing Requirements for DCANx Receive
          2. Table 5-19 Switching Characteristics for DCANx Transmit
      6. 5.12.6  DMTimer
        1. 5.12.6.1 DMTimer Electrical Data and Timing
          1. Table 5-20 Timing Requirements for DMTimer [1-11]
          2. Table 5-21 Switching Characteristics for DMTimer [4-7]
      7. 5.12.7  Ethernet Media Access Controller (EMAC) and Switch
        1. 5.12.7.1 Ethernet MAC and Switch Electrical Data and Timing
          1. Table 5-22 Ethernet MAC and Switch Timing Conditions
          2. 5.12.7.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing
            1. Table 5-23 Timing Requirements for MDIO_DATA
            2. Table 5-24 Switching Characteristics for MDIO_CLK
            3. Table 5-25 MDIO Switching Characteristics - MDIO_DATA
          3. 5.12.7.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
            1. Table 5-26 Timing Requirements for GMII[x]_RXCLK - MII Mode
            2. Table 5-27 Timing Requirements for GMII[x]_TXCLK - MII Mode
            3. Table 5-28 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
            4. Table 5-29 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
          4. 5.12.7.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing
            1. Table 5-30 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-31 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-32 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          5. 5.12.7.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
            1. Table 5-33 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-34 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-35 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-36 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
      8. 5.12.8  External Memory Interfaces
        1. 5.12.8.1 General-Purpose Memory Controller (GPMC)
          1. 5.12.8.1.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-37 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-38 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-39 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.12.8.1.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-40 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
            2. Table 5-41 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-42 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            4. Table 5-43 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.12.8.1.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-44 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
            2. Table 5-45 GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-46 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            4. Table 5-47 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        2. 5.12.8.2 Memory Interface
          1. 5.12.8.2.1 DDR3 and DDR3L Routing Guidelines
            1. 5.12.8.2.1.1 Board Designs
            2. 5.12.8.2.1.2 DDR3 Device Combinations
            3. 5.12.8.2.1.3 DDR3 Interface
              1. 5.12.8.2.1.3.1  DDR3 Interface Schematic
              2. 5.12.8.2.1.3.2  Compatible JEDEC DDR3 Devices
              3. 5.12.8.2.1.3.3  DDR3 PCB Stackup
              4. 5.12.8.2.1.3.4  DDR3 Placement
              5. 5.12.8.2.1.3.5  DDR3 Keepout Region
              6. 5.12.8.2.1.3.6  DDR3 Bulk Bypass Capacitors
              7. 5.12.8.2.1.3.7  DDR3 High-Speed Bypass Capacitors
                1. 5.12.8.2.1.3.7.1 Return Current Bypass Capacitors
              8. 5.12.8.2.1.3.8  DDR3 Net Classes
              9. 5.12.8.2.1.3.9  DDR3 Signal Termination
              10. 5.12.8.2.1.3.10 DDR3 DDR_VREF Routing
              11. 5.12.8.2.1.3.11 DDR3 VTT
            4. 5.12.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
              1. 5.12.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16)
                1. 5.12.8.2.1.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 5.12.8.2.1.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              2. 5.12.8.2.1.4.2 Using Four 8-Bit DDR3 Devices
                1. 5.12.8.2.1.4.2.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 5.12.8.2.1.4.2.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              3. 5.12.8.2.1.4.3 One 16-Bit DDR3 Device
                1. 5.12.8.2.1.4.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 5.12.8.2.1.4.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
            5. 5.12.8.2.1.5 Data Topologies and Routing Definition
              1. 5.12.8.2.1.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
              2. 5.12.8.2.1.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
            6. 5.12.8.2.1.6 Routing Specification
              1. 5.12.8.2.1.6.1 CK and ADDR_CTRL Routing Specification
              2. 5.12.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification
          2. 5.12.8.2.2 LPDDR2 Routing Guidelines
            1. 5.12.8.2.2.1 LPDDR2 Board Designs
            2. 5.12.8.2.2.2 LPDDR2 Device Configurations
            3. 5.12.8.2.2.3 LPDDR2 Interface
              1. 5.12.8.2.2.3.1 LPDDR2 Interface Schematic
              2. 5.12.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices
              3. 5.12.8.2.2.3.3 LPDDR2 PCB Stackup
              4. 5.12.8.2.2.3.4 LPDDR2 Placement
              5. 5.12.8.2.2.3.5 LPDDR2 Keepout Region
              6. 5.12.8.2.2.3.6 LPDDR2 Net Classes
              7. 5.12.8.2.2.3.7 LPDDR2 Signal Termination
              8. 5.12.8.2.2.3.8 LPDDR2 DDR_VREF Routing
            4. 5.12.8.2.2.4 Routing Specification
              1. 5.12.8.2.2.4.1 DQS[x] and DQ[x] Routing Specification
              2. 5.12.8.2.2.4.2 CK and ADDR_CTRL Routing Specification
      9. 5.12.9  Display Subsystem (DSS)
        1. 5.12.9.1 DSS—Parallel Interface
          1. 5.12.9.1.1 DSS—Parallel Interface—Bypass Mode
            1. 5.12.9.1.1.1 DSS—Parallel Interface—Bypass Mode—TFT Mode
            2. 5.12.9.1.1.2 DSS—Parallel Interface—Bypass Mode—STN Mode
          2. 5.12.9.1.2 DSS—Parallel Interface—RFBI Mode—Applications
            1. 5.12.9.1.2.1 DSS—Parallel Interface—RFBI Mode—MIPI DBI 2.0—LCD Panel
            2. 5.12.9.1.2.2 DSS—Parallel Interface—RFBI Mode—Pico DLP
      10. 5.12.10 Camera (VPFE)
        1. 5.12.10.1 Camera (VPFE) Timing
          1. Table 5-80 VPFE Timing Requirements
          2. Table 5-81 VPFE Output Switching Characteristics
      11. 5.12.11 Inter-Integrated Circuit (I2C)
        1. 5.12.11.1 I2C Electrical Data and Timing
          1. Table 5-82 I2C Timing Conditions - Slave Mode
          2. Table 5-83 Timing Requirements for I2C Input Timings
          3. Table 5-84 Switching Characteristics for I2C Output Timings
      12. 5.12.12 Multichannel Audio Serial Port (McASP)
        1. 5.12.12.1 McASP Device-Specific Information
        2. 5.12.12.2 McASP Electrical Data and Timing
          1. Table 5-85 McASP Timing Conditions
          2. Table 5-86 Timing Requirements for McASP
          3. Table 5-87 Switching Characteristics for McASP
      13. 5.12.13 Multichannel Serial Port Interface (McSPI)
        1. 5.12.13.1 McSPI Electrical Data and Timing
          1. 5.12.13.1.1 McSPI—Slave Mode
            1. Table 5-88 McSPI Timing Conditions—Slave Mode
            2. Table 5-89 Timing Requirements for McSPI Input Timings—Slave Mode
            3. Table 5-90 Switching Characteristics for McSPI Output Timings—Slave Mode
          2. 5.12.13.1.2 McSPI—Master Mode
            1. Table 5-91 McSPI Timing Conditions—Master Mode
            2. Table 5-92 Timing Requirements for McSPI Input Timings—Master Mode
            3. Table 5-93 Switching Characteristics for McSPI Output Timings—Master Mode
      14. 5.12.14 Quad Serial Port Interface (QSPI)
        1. Table 5-94 QSPI Switching Characteristics
      15. 5.12.15 HDQ/1-Wire Interface (HDQ/1-Wire)
        1. 5.12.15.1 HDQ Protocol
        2. 5.12.15.2 1-Wire Protocol
      16. 5.12.16 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
        1. 5.12.16.1 Programmable Real-Time Unit (PRU-ICSS PRU)
          1. Table 5-99  PRU-ICSS PRU Timing Conditions
          2. 5.12.16.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
            1. Table 5-100 PRU-ICSS PRU Timing Requirements - Direct Input Mode
            2. Table 5-101 PRU-ICSS PRU Switching Requirements - Direct Output Mode
          3. 5.12.16.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
            1. Table 5-102 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
          4. 5.12.16.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
            1. Table 5-103 PRU-ICSS PRU Timing Requirements - Shift In Mode
            2. Table 5-104 PRU-ICSS PRU Switching Requirements - Shift Out Mode
          5. 5.12.16.1.4 PRU-ICSS Sigma Delta Electrical Data and Timing
            1. Table 5-105 PRU-ICSS Timing Requirements - Sigma Delta Mode
          6. 5.12.16.1.5 PRU-ICSS ENDAT Electrical Data and Timing
            1. Table 5-106 PRU-ICSS Timing Requirements - ENDAT Mode
            2. Table 5-107 PRU-ICSS Switching Requirements - ENDAT Mode
        2. 5.12.16.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
          1. Table 5-108 PRU-ICSS ECAT Timing Conditions
          2. 5.12.16.2.1 PRU-ICSS ECAT Electrical Data and Timing
            1. Table 5-109 PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
            2. Table 5-110 PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
            3. Table 5-111 PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
            4. Table 5-112 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
            5. Table 5-113 PRU-ICSS ECAT Switching Requirements - Digital IOs
        3. 5.12.16.3 PRU-ICSS MII_RT and Switch
          1. Table 5-114 PRU-ICSS MII_RT Switch Timing Conditions
          2. 5.12.16.3.1 PRU-ICSS MDIO Electrical Data and Timing
            1. Table 5-115 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
            2. Table 5-116 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
            3. Table 5-117 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
          3. 5.12.16.3.2 PRU-ICSS MII_RT Electrical Data and Timing
            1. Table 5-118 PRU-ICSS MII_RT Timing Requirements - MII_RXCLK
            2. Table 5-119 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
            3. Table 5-120 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
            4. Table 5-121 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
        4. 5.12.16.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
          1. Table 5-122 Timing Requirements for PRU-ICSS UART Receive
          2. Table 5-123 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      17. 5.12.17 Multimedia Card (MMC) Interface
        1. 5.12.17.1 MMC Electrical Data and Timing
          1. Table 5-124 MMC Timing Conditions
          2. Table 5-125 Timing Requirements for MMC[0]_CMD and MMC[0]_DAT[7:0]
          3. Table 5-126 Timing Requirements for MMC[1/2]_CMD and MMC[1/2]_DAT[7:0]
          4. Table 5-127 Switching Characteristics for MMC[x]_CLK
          5. Table 5-128 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=0
          6. Table 5-129 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=1
      18. 5.12.18 Universal Asynchronous Receiver/Transmitter (UART)
        1. 5.12.18.1 UART Electrical Data and Timing
          1. Table 5-130 Timing Requirements for UARTx Receive
          2. Table 5-131 for UARTx Transmit
        2. 5.12.18.2 UART IrDA Interface
    13. 5.13 Emulation and Debug
      1. 5.13.1 IEEE 1149.1 JTAG
        1. 5.13.1.1 JTAG Electrical Data and Timing
          1. Table 5-134 Timing Requirements for JTAG
          2. Table 5-135 Switching Characteristics for JTAG
  6. 6Device and Documentation Support
    1. 6.1 Device Nomenclature
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Related Links
    5. 6.5 Community Resources
    6. 6.6 Trademarks
    7. 6.7 Electrostatic Discharge Caution
    8. 6.8 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Via Channel
    2. 7.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZDN|491
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1.1 Features

  • Highlights
    • Sitara™ARM® Cortex®-A9 32-Bit RISC Processor With Processing Speed up to 1000 MHz
      • NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor
      • 32KB of Both L1 Instruction and Data Cache
      • 256KB of L2 Cache or L3 RAM
    • 32-Bit LPDDR2, DDR3, and DDR3L Support
    • General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECC
    • SGX530 Graphics Engine
    • Display Subsystem
    • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Real-Time Clock (RTC)
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • 10, 100, and 1000 Ethernet Switch Supporting up to Two Ports
    • Serial Interfaces:
      • Two Controller Area Network (CAN) Ports
      • Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-Wire
    • Security
      • Crypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)
      • Secure Boot (Avaliable Only on AM437x High-Security [AM437xHS] Devices)
    • Two 12-Bit Successive Approximation Register (SAR) ADCs
    • Up to Three 32-Bit Enhanced Capture (eCAP) Modules
    • Up to Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
    • Up to Six Enhanced High-Resolution PWM (eHRPWM) Modules
  • MPU Subsystem
    • ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 1000 MHz
    • 32KB of Both L1 Instruction and Data Cache
    • 256KB of L2 Cache (Option to Configure as L3 RAM)
    • 256KB of On-Chip Boot ROM
    • 64KB of On-Chip RAM
    • Secure Control Module (SCM) (Avaliable Only on AM437xHS Devices)
    • Emulation and Debug
      • JTAG
      • Embedded Trace Buffer
    • Interrupt Controller
  • On-Chip Memory (Shared L3 RAM)
    • 256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
    • Up to 512KB of Total Internal RAM
      (256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)
  • External Memory Interfaces (EMIFs)
    • DDR Controllers:
      • LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
      • DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)
      • 32-Bit Data Bus
      • 2GB of Total Addressable Space
      • Supports One x32, Two x16, or Four x8 Memory Device Configurations
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
  • Error Locator Module (ELM)
    • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
    • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS®, PROFINET®, and EtherNet/IP™, EnDat 2.2, and More
    • Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores Each
      • Each Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz
      • 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity)
      • 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal
    • 12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller Module (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One eCAP Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
    • Industrial Communication is Supported by Two PRU-ICSS Subsystems
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], and LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (RTC and Wake-Up Logic [WAKE-UP])
      • Three Switchable Power Domains (MPU Subsystem, SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO
    • Independent Power-On-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (RTC_WAKEUP) for External Wake Events
    • Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup or Cortex-A9 for Event Notification
    • Programmable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enable the Power-Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs
      (10, 100, and 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, and RGMII and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v2 Precision Time Protocol (PTP)
    • Up to Two CAN Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins Per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Five Master and Slave McSPIs
      • McSPI0–McSPI2 Support up to Four Chip Selects
      • McSPI3 and McSPI4 Support up to Two Chip Selects
      • Up to 48 MHz
    • One Quad-SPI
      • Supports eXecute In Place (XIP) from Serial NOR FLASH
    • One Dallas 1-Wire® and HDQ Serial Interface
    • Up to Three MMC, SD, and SDIO Ports
      • 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes
      • 1.8- or 3.3-V Operation on All Ports
      • Up to 48-MHz Clock
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3 and SD and SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Six Banks of General-Purpose I/O (GPIO)
      • 32 GPIOs per Bank (Multiplexed With Other Functional Pins)
      • GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs
    • Twelve 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Public Watchdog Timer
    • One Free-Running, High-Resolution 32-kHz Counter (synctimer32K)
    • One Secure Watchdog Timer (Avaliable Only on AM437xHS Devices)
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20M Poly/sec
      • Universal Scalable Shader Engine is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • Display Subsystem
      • Display Modes
        • Programmable Pixel Memory Formats (Palletized: 1-, 2-, 4-, and 8-Bits Per Pixel; RGB 16- and 24-Bits Per Pixel; and YUV 4:2:2)
        • 256- × 24-Bit Entries Palette in RGB
        • Up to 2048 × 2048 Resolution
      • Display Support
        • Four Types of Displays Are Supported: Passive and Active Colors; Passive and Active Monochromes
        • 4- and 8-Bit Monochrome Passive Panel Interface Support (15 Grayscale Levels Supported Using Dithering Block)
        • RGB 8-Bit Color Passive Panel Interface Support (3,375 Colors Supported for Color Panel Using Dithering Block)
        • RGB 12-, 16-, 18-, and 24-Bit Active Panel Interface Support (Replicated or Dithered Encoded Pixel Values)
        • Remote Frame Buffer (Embedded in the LCD Panel) Support Through the RFBI Module
        • Partial Refresh of the Remote Frame Buffer Through the RFBI Module
        • Partial Display
        • Multiple Cycles Output Format on 8-, 9-, 12-, and 16-Bit Interface (TDM)
      • Signal Processing
        • Overlay and Windowing Support for One Graphics Layer (RGB or CLUT) and Two Video Layers (YUV 4:2:2, RGB16, and RGB24)
        • RGB 24-Bit Support on the Display Interface, Optionally Dithered to RGB 18‑Bit Pixel Output Plus 6-Bit Frame Rate Control (Spatial and Temporal)
        • Transparency Color Key (Source and Destination)
        • Synchronized Buffer Update
        • Gamma Curve Support
        • Multiple-Buffer Support
        • Cropping Support
        • Color Phase Rotation
    • Two 12-Bit SAR ADCs (ADC0, ADC1)
      • 867K Samples Per Second
      • Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • ADC0 Can Be Configured to Operate as a 4‑, 5-, or 8-Wire Resistive Touch Screen Controller (TSC)
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Six Enhanced eHRPWM Modules
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit eQEP Modules
  • Device Identification
    • Factory Programmable Electrical Fuse Farm (FuseFarm)
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
      • Security Keys (Avaliable Only on AM437xHS Devices)
      • Feature Identification
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug
    • Supports Real-Time Trace Pins (for Cortex-A9)
    • 64-KB Embedded Trace Buffer (ETB)
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels
    • EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, and Slave Peripherals)
  • InterProcessor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Camera
    • Dual Port 8- and 10-Bit BT656 Interface
    • Dual Port 8- and 10-Bit Including External Syncs
    • Single Port 12-Bit
    • YUV422/RGB422 and BT656 Input Format
    • RAW Format
    • Pixel Clock Rate up to 75 MHz
  • Package
    • 491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost Routing