22.214.171.124.2.3.4 LPDDR2 Placement
Figure 5-81 shows the placement rules for the device as well as the LPDDR2 memory device. Placement restrictions are provided as a guidance to restrict maximum trace lengths and allow for proper routing space.
Figure 5-81 Placement Specifications
Table 5-65 Placement Specifications(1)
||Clearance from non-LPDDR2 signal to LPDDR2 keepout region(4)(5)
- LPDDR2 keepout region to encompass entire LPDDR2 routing area.
- Measurements from center of device to center of LPDDR2 device.
- Minimizing X1 and Y improves timing margins.
- w is defined as the signal trace width.
- Non-LPDDR2 signals allowed within LPDDR2 keepout region provided they are separated from LPDDR2 routing layers by a ground plane.