Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL, a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.
It is not required, nor is it recommended, to match the lengths across all bytes. Length matching is only required within each byte.
Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-28 shows this distance for four loads. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 7-14.
|DRS36||DQSn+ to DQSn- skew||1||ps|
|DRS37||DQSn to DBn skew(3)(4)||5(10)||ps|
|DRS38||Vias per trace||2(1)||vias|
|DRS39||Via count difference||0(10)||vias|
|DRS310||Center-to-center DBn to other DDR3 trace spacing(6)||4||w(5)|
|DRS311||Center-to-center DBn to other DBn trace spacing(7)||3||w(5)|
|DRS312||DQSn center-to-center spacing(8)(9)|
|DRS313||DQSn center-to-center spacing to other net||4||w(5)|