SPRS961F August   2016  – November 2019 AM5706 , AM5708


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 Emulation and Debug Subsystem
      25. 4.3.25 System and Miscellaneous
        1. Sysboot
        2. Power, Reset, and Clock Management (PRCM)
        3. System Direct Memory Access (SDMA)
        4. Interrupt Controllers (INTC)
      26. 4.3.26 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
        1. Table 5-4 Voltage Domains Operating Performance Points
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-7  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-8  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-9  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-11 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-12 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. Parameter Information
          1. 1.8 V and 3.3 V Signal Transition Levels
          2. 1.8 V and 3.3 V Signal Transition Rates
          3. Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. Interface Clock Terminology
        2. Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. Input Clocks / Oscillators
          1. OSC0 External Crystal
          2. OSC0 Input Clock
          3. Auxiliary Oscillator OSC1 Input Clock
            1. OSC1 External Crystal
            2. OSC1 Input Clock
          4. RC On-die Oscillator Clock
        2. Output Clocks
        3. DPLLs, DLLs
          1. DPLL Characteristics
          2. DLL Characteristics
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1.  Timing Test Conditions
        2.  Virtual and Manual I/O Timing Modes
        3.  VIP
        4.  DSS
        5.  HDMI
        6.  CSI2
          1. CSI-2 MIPI D-PHY
        7.  EMIF
        8.  GPMC
          1. GPMC/NOR Flash Interface Synchronous Timing
          2. GPMC/NOR Flash Interface Asynchronous Timing
          3. GPMC/NAND Flash Interface Asynchronous Timing
        9.  Timers
        10. I2C
          1. Table 5-57 Timing Requirements for I2C Input Timings
          2. Table 5-58 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-59 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. HDQ1W
          1. HDQ / 1-Wire — HDQ Mode
          2. HDQ/1-Wire—1-Wire Mode
        12. UART
          1. Table 5-64 Timing Requirements for UART
          2. Table 5-65 Switching Characteristics Over Recommended Operating Conditions for UART
        13. McSPI
        14. QSPI
        15. McASP
          1. Table 5-72 Timing Requirements for McASP1
          2. Table 5-73 Timing Requirements for McASP2
          3. Table 5-74 Timing Requirements for McASP3/4/5/6/7/8
        16. USB
          1. USB1 DRD PHY
          2. USB2 PHY
        17. PCIe
        18. DCAN
          1. Table 5-89 Timing Requirements for DCANx Receive
          2. Table 5-90 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. GMAC_SW
          1. GMAC MII Timings
            1. Table 5-91 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-92 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-93 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-94 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. GMAC MDIO Interface Timings
          3. GMAC RMII Timings
            1. Table 5-99  Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-100 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-101 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. GMAC RGMII Timings
            1. Table 5-106 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-107 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-108 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-109 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. eMMC/SD/SDIO
          1. MMC1—SD Card Interface
            1. Default speed, 4-bit data, SDR, half-cycle
            2. High speed, 4-bit data, SDR, half-cycle
            3. SDR12, 4-bit data, half-cycle
            4. SDR25, 4-bit data, half-cycle
            5. UHS-I SDR50, 4-bit data, half-cycle
            6. UHS-I SDR104, 4-bit data, half-cycle
            7. UHS-I DDR50, 4-bit data
          2. MMC2 — eMMC
            1. Standard JC64 SDR, 8-bit data, half cycle
            2. High-speed JC64 SDR, 8-bit data, half cycle
            3. High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. High-speed JC64 DDR, 8-bit data
              1. Table 5-134 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. MMC3 and MMC4—SDIO/SD
            1. MMC3 and MMC4, SD Default Speed
            2. MMC3 and MMC4, SD High Speed
            3. MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. MMC3 and MMC4, SD SDR25 Mode
            5. MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        21. GPIO
        22. PRU-ICSS
          1. Programmable Real-Time Unit (PRU-ICSS PRU)
            1. PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-156 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-157 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-158 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-159 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-160 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-161 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-162 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-163 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-164 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-165 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-166 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-167 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-168 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. PRU-ICSS MII_RT and Switch
            1. PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-169 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-170 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-171 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-173 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-174 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-175 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-176 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-177 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. PRU-ICSS IOSETs
          6. PRU-ICSS Manual Functional Mapping
        23. System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. JTAG Electrical Data/Timing
            1. Table 5-194 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-195 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-196 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-197 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. Trace Port Interface Unit (TPIU)
          1. TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  PRU-ICSS
    6. 6.6  Memory Subsystem
      1. 6.6.1 EMIF
      2. 6.6.2 GPMC
      3. 6.6.3 ELM
      4. 6.6.4 OCMC
    7. 6.7  Interprocessor Communication
      1. 6.7.1 MailBox
      2. 6.7.2 Spinlock
    8. 6.8  Interrupt Controller
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  VIP
      2. 6.10.2  DSS
      3. 6.10.3  Timers
        1. General-Purpose Timers
        2. 32-kHz Synchronized Timer (COUNTER_32K)
        3. Watchdog Timer
      4. 6.10.4  I2C
      5. 6.10.5  UART
        1. UART Features
        2. IrDA Features
        3. CIR Features
      6. 6.10.6  McSPI
      7. 6.10.7  QSPI
      8. 6.10.8  McASP
      9. 6.10.9  USB
      10. 6.10.10 PCIe
      11. 6.10.11 DCAN
      12. 6.10.12 GMAC_SW
      13. 6.10.13 eMMC/SD/SDIO
      14. 6.10.14 GPIO
      15. 6.10.15 ePWM
      16. 6.10.16 eCAP
      17. 6.10.17 eQEP
    11. 6.11 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 DDR3 Board Design and Layout Guidelines
      1. 7.2.1 DDR3 General Board Layout Guidelines
      2. 7.2.2 DDR3 Board Design and Layout Guidelines
        1.  Board Designs
        2.  DDR3 EMIF
        3.  DDR3 Device Combinations
        4.  DDR3 Interface Schematic
          1. 32-Bit DDR3 Interface
          2. 16-Bit DDR3 Interface
        5.  Compatible JEDEC DDR3 Devices
        6.  PCB Stackup
        7.  Placement
        8.  DDR3 Keepout Region
        9.  Bulk Bypass Capacitors
        10. High-Speed Bypass Capacitors
          1. Return Current Bypass Capacitors
        11. Net Classes
        12. DDR3 Signal Termination
        13. VREF_DDR Routing
        14. VTT
        15. CK and ADDR_CTRL Topologies and Routing Definition
          1. Four DDR3 Devices
            1. CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. Two DDR3 Devices
            1. CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. One DDR3 Device
            1. CK and ADDR_CTRL Topologies, One DDR3 Device
            2. CK and ADDR/CTRL Routing, One DDR3 Device
        16. Data Topologies and Routing Definition
          1. DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. Routing Specification
          1. CK and ADDR_CTRL Routing Specification
          2. DQS and DQ Routing Specification
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 Power Distribution Network Implementation Guidance
    5. 7.5 Thermal Solution Guidance
    6. 7.6 Single-Ended Interfaces
      1. 7.6.1 General Routing Guidelines
      2. 7.6.2 QSPI Board Design and Layout Guidelines
    7. 7.7 LJCB_REFN/P Connections
    8. 7.8 Clock Routing Guidelines
      1. 7.8.1 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CBD|538
Thermal pad, mechanical data (Package|Pins)
Orderable Information

DSP Subsystem

The device includes a single instance (DSP1) of a digital signal processor (DSP) subsystem, based on the TI's standard TMS320C66x DSP CorePac core.

The TMS320C66x DSP core enhances the TMS320C674x™ core, which merges the C674x™ floating point and the C64x+™ fixed-point instruction set architectures. The C66x DSP is object-code compatible with the C64x+/C674x DSPs.

For more information on the TMS320C66x core CPU, see the TMS320C66x DSP CPU and Instruction Set Reference Guide, (SPRUGH7).

The DSP subsystem integrated in the device includes the following components:

  • A TMS320C66x CorePac DSP core that encompasses:
    • L1 program-dedicated (L1P) cacheable memory
    • L1 data-dedicated (L1D) cacheable memory
    • L2 (program and data) cacheable memory
    • Extended Memory Controller (XMC)
    • External Memory Controller (EMC)
    • DSP CorePac located interrupt controller (INTC)
    • DSP CorePac located power-down controller (PDC)
  • Dedicated enhanced data memory access engine - EDMA, to transfer data from/to memories and peripherals external to the DSP subsystem and to local DSP memory (most commonly L2 SRAM). The external DMA requests are passed through DSP system level (SYS) wakeup logic, and collected from the DSP1 dedicated outputs of the device DMA Events Crossbar for the subsystem.
  • A level 2 (L2) interconnect network (DSP NoC) to allow connectivity between different modules of the subsystem or the remainder of the device via the device L3_MAIN interconnect.
  • Two memory management units (on EDMA L2 interconnect and DSP MDMA paths) for accessing the device L3_MAIN interconnect address space
  • Dedicated system control logic (DSP_SYSTEM) responsible for power management, clock generation, and connection to the device power, reset, and clock management (PRCM) module

The TMS320C66x Instruction Set Architecture (ISA) is the latest for the C6000 family. As with its predecessors (C64x, C64x+ and C674x), the C66x is an advanced VLIW architecture with 8 functional units (two multiplier units and six arithmetic logic units) that operate in parallel. The C66x CPU has a total of 64 general-purpose 32-bit registers.

Some features of the DSP C6000 family devices are:

  • Advanced VLIW CPU with eight functional units (two multipliers and six ALUs) which:
    • Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
    • Allows designers to develop highly effective RISC-like code for fast development time
  • Instruction packing
    • Gives code size equivalence for eight instructions executed serially or in parallel
    • Reduces code size, program fetches, and power consumption
  • Conditional execution of most instructions
    • Reduces costly branching
    • Increases parallelism for higher sustained performance
  • Efficient code execution on independent functional units
    • Industry's most efficient C compiler on DSP benchmark suite
    • Industry's first assembly optimizer for fast development and improved parallelization
  • 8-/16-/32-bit/64-bit data support, providing efficient memory support for a variety of applications
  • 40-bit arithmetic options which add extra precision for vocoders and other computationally intensive applications
  • Saturation and normalization to provide support for key arithmetic operations
  • Field manipulation and instruction extract, set, clear, and bit counting support common operation found in control and data manipulation applications.

The C66x CPU has the following additional features:

  • Each multiplier can perform two 16 × 16-bit or four 8 × 8 bit multiplies every clock cycle.
  • Quad 8-bit and dual 16-bit instruction set extensions with data flow support
  • Support for non-aligned 32-bit (word) and 64-bit (double word) memory accesses
  • Special communication-specific instructions have been added to address common operations in error-correcting codes.
  • Bit count and rotate hardware extends support for bit-level algorithms.
  • Compact instructions: Common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce code size.
  • Protected mode operation: A two-level system of privileged program execution to support higher-capability operating systems and system features such as memory protection.
  • Exceptions support for error detection and program redirection to provide robust code execution
  • Hardware support for modulo loop operation to reduce code size and allow interrupts during fully-pipelined code
  • Each multiplier can perform 32 × 32 bit multiplies
  • Additional instructions to support complex multiplies allowing up to eight 16-bit multiply/add/subtracts per clock cycle

The TMS320C66x has the following key improvements to the ISA:

  • 4x Multiply Accumulate improvement for both fixed and floating point
  • Improvement of the floating point arithmetic
  • Enhancement of the vector processing capability for fixed and floating point
  • Addition of domain-specific instructions for complex arithmetic and matrix operations

On the C66x ISA, the vector processing capability is improved by extending the width of the SIMD instructions. The C674x DSP supports 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. C66x enhances this capabilities with the addition of SIMD instructions for 32-bit data allowing operation on 128-bit vectors. For example the QMPY32 instruction is able to perform the element to element multiplication between two vectors of four 32-bit data each.

C66x ISA includes a set of specific instructions to handle complex arithmetic and matrix operations.

  • TMS320C66x DSP CorePac memory components:
    • A 32-KiB L1 program memory (L1P) configurable as cache and/or SRAM:
      • When configured as a cache, the L1P is a 1-way set-associative cache with a 32-byte cache line
      • The DSP CorePac L1P memory controller provides bandwidth management, memory protection, and power-down functions
      • The L1P is capable of cache block and global coherence operations
      • The L1P controller has an Error Detection (ED) mechanism, including necessary SRAM
      • The L1P memory can be fully configured as a cache or SRAM
      • Page size for L1P memory is 2KB
    • A 32-KiB L1 data memory (L1D) configurable as cache and / or SRAM:
      • When configured as a cache, the L1D is a 2-way set-associative cache with a 64-byte cache line
      • The DSP CorePac L1D memory controller provides bandwidth management, memory protection, and power-down functions
      • The L1D memory can be fully configured as a cache or SRAM
      • No support for error correction or detection
      • Page size for L1D memory is 2KB
    • A 288-KiB (program and data) L2 memory, only part of which is cacheable:
      • When configured as a cache, the L2 memory is a 4-way set associative cache with a 128-byte cache line
      • Only 256 KiB of L2 memory can be configured as cache or SRAM
      • 32 KiB of the L2 memory is always mapped as SRAM
      • The L2 memory controller has an Error Correction Code (ECC) and ED mechanism, including necessary SRAM
      • The L2 memory controller supports hardware prefetching and also provides bandwidth management, memory protection, and power-down functions.
      • Page size for L2 memory is 16KB
  • The External Memory Controller (EMC) is a bridge from the C66x CorePac to the rest of the DSP subsystem and device. It has :
    • a 32-bit configuration port (CFG) providing access to local subsystem resources (like DSP_EDMA, DSP_SYSTEM, and so forth) or to L3_MAIN resources accessible via the CFG address range.
    • a 128-bit slave-DMA port (SDMA) which provides accesses of system masters outside the DSP subsystem to resources inside the DSP subsystem or C66x DSP CorePac memories, i.e. when the DSP subsystem is the slave in a transaction.
  • The Extended Memory Controller (XMC) processes requests from the L2 Cache Controller (which are a result of CPU instruction fetches, load/store commands, cache operations) to device resources via the C66x DSP CorePac 128-bit master DMA (MDMA) port:
    • Memory protection for addresses outside C66x DSP CorePac generated over device L3_MAIN on the MDMA port
    • Prefetch, multi-in-flight requests
  • A DSP local Interrupt Controller (INTC) in the DSP C66x CorePac, interfaces the system events to the DSP C66x core CPU interrupt and exceptions inputs. The DSP subsystem C66x CorePac interrupt controller supports up to 128 system events of which 64 interrupts are external to DSP subsystem, collected from the DSP1 dedicated outputs of the device Interrupt Crossbar.
  • Local Enhanced Direct Memory Access (EDMA) controller features:
    • Channel controller (CC) : 64-channel, 128 PaRAM, 2 Queues
    • 2 x Third-party Transfer Controllers (TPTC0 and TPTC1):
      • Each TC has a 128-bit read port and a 128-bit write port
      • 2KiB FIFOs on each TPTC
    • 1-dimensional/2-dimensional (1D/2D) addressing
    • Chaining capability
  • DSP subsystem integrated MMUs:
    • Two MMUs are integrated:
      • The MMU0 is located between DSP MDMA master port and the device L3_MAIN interconnect and can be optionally bypassed
      • The MMU1 is located between the EDMA master port and the device L3_MAIN interconnect
  • A DSP local Power-Down Controller (PDC) is responsible to power-down various parts of the DSP C66x CorePac, or the entire DSP C66x CorePac.
  • The DSP subsystem System Control logic provides:
    • Slave idle and master standby protocols with device PRCM for powerdown
    • OCP Disconnect handshake for init and target busses
    • Asynchronous reset
    • Power-down modes:
      • "Clockstop" mode featuring wake-up on interrupt event. The DMA event wake-up is managed in software.
  • The device DSP subsystem is supplied by a PRCM DPLL, but DSP1 has integrated its own PLL module outside the C66x CorePac for clock gating and division.
  • The device DSP subsystem has following port instances to connect to remaining part of the device. See also :
    • A 128-bit initiator (DSP MDMA master) port for MDMA/Cache requests
    • A 128-bit initiator (DSP EDMA master) port for EDMA requests
    • A 32-bit initiator (DSP CFG master) port for configuration requests
    • A 128-bit target (DSP slave) port for requests to DSP memories and various peripherals
  • C66x DSP subsystem (DSPSS) safety aspects:
    • Above mentioned memory ECC/ED mechanisms
    • MMUs enable mapping of only the necessary application space to the processor
    • Memory Protection Units internal to the DSPSS (in L1P, L1D and L2 memory controllers) and external to DSPSS (firewalls) to help define legal accesses and raise exceptions on illegal accesses
    • Exceptions: Memory errors, various DSP errors, MMU errors and some system errors are detected and cause exceptions. The exceptions could be handled by the DSP or by a designated safety processor at the chip level. Note that it may not be possible for the safety processor to completely handle some exceptions

Unsupported features on the C66x DSP core for the device are:

  • The Extended Memory Controller MPAX (memory protection and address extension) 36-bit addressing is NOT supported

Known DSP subsystem powermode restrictions for the device are:

  • "Full logic / RAM retention" mode featuring wake-up on both interrupt or DMA event (logic in “always on” domain). Only OFF mode is supported by DSP subsystem, requiring full boot.

Fore more information about:

  • C66x debug/trace support, see chapter On-Chip Debug of the Device TRM.