The device has a large number of interrupts to service the needs of its many peripherals and subsystems. The MPU, DSP, and IPU (x2) subsystems are capable of servicing these interrupts via their integrated interrupt controllers. In addition, each processor's interrupt controller is preceded by an Interrupt Controller Crossbar (IRQ_CROSSBAR) that provides flexibility in mapping the device interrupts to processor interrupt inputs. For more information about IRQ crossbar, see chapter Control Module of the Device TRM.
Cortex®-A15 MPU Subsystem Interrupt Controller (MPU_INTC)
The MPU_INTC module (also called Generalized Interrupt Controller [GIC]) is a single functional unit that is integrated in the Arm® Cortex-A15 multiprocessor core (MPCore) alongside Cortex-A15 processor. It provides:
The Cortex-A15 processor supports three main groups of interrupt sources, with each interrupt source having a unique ID:
For detailed information about this module and description of SGIs and PPIs, see the Arm Cortex-A15 MPCore Technical Reference Manual (available at infocenter.arm.com/help/index.jsp).
C66x DSP Subsystem Interrupt Controller (DSP1_INTC)
The DSP1 subsystem integrates an interrupt controller - DSP1_INTC, which interfaces the system events to the C66x core interrupt and exceptions inputs. It combines up to 128 interrupts into 12 prioritized interrupts presented to the C66x CPU.
For detailed information about this module, see chapter DSP Subsystem of the Device TRM.
Dual Cortex-M4 IPU Subsystem Interrupt Controller (IPUx_Cx_INTC, where x = 1, 2)
There are two Image Processing Unit (IPU) subsystems in the device - IPU1, and IPU2. Each IPU subsystem integrates two Arm Cortex-M4 cores.
A Nested Vectored Interrupt Controller (NVIC) is integrated within each Cortex-M4. The interrupt mapping is the same (per IPU) for the two cores to facilitate parallel processing. The NVIC supports:
For detailed information about this module, refer to Arm Cortex-M4 Technical Reference Manual (available at infocenter.arm.com/help/index.jsp).