SPRSP56F January   2021  – October 2023 AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      12
      2.      13
    3. 6.3 Signal Descriptions
      1.      15
      2. 6.3.1  ADC
        1. 6.3.1.1 MAIN Domain
          1.        18
      3. 6.3.2  CPSW3G
        1. 6.3.2.1 MAIN Domain
          1.        21
          2.        22
          3.        23
      4. 6.3.3  CPTS
        1. 6.3.3.1 MAIN Domain
          1.        26
          2.        27
      5. 6.3.4  DDRSS
        1. 6.3.4.1 MAIN Domain
          1.        30
      6. 6.3.5  ECAP
        1. 6.3.5.1 MAIN Domain
          1.        33
          2.        34
          3.        35
      7. 6.3.6  Emulation and Debug
        1. 6.3.6.1 MAIN Domain
          1.        38
        2. 6.3.6.2 MCU Domain
          1.        40
      8. 6.3.7  EPWM
        1. 6.3.7.1 MAIN Domain
          1.        43
          2.        44
          3.        45
          4.        46
          5.        47
          6.        48
          7.        49
          8.        50
          9.        51
          10.        52
      9. 6.3.8  EQEP
        1. 6.3.8.1 MAIN Domain
          1.        55
          2.        56
          3.        57
      10. 6.3.9  FSI
        1. 6.3.9.1 MAIN Domain
          1.        60
          2.        61
          3.        62
          4.        63
          5.        64
          6.        65
          7.        66
          8.        67
      11. 6.3.10 GPIO
        1. 6.3.10.1 MAIN Domain
          1.        70
          2.        71
        2. 6.3.10.2 MCU Domain
          1.        73
      12. 6.3.11 GPMC
        1. 6.3.11.1 MAIN Domain
          1.        76
      13. 6.3.12 I2C
        1. 6.3.12.1 MAIN Domain
          1.        79
          2.        80
          3.        81
          4.        82
        2. 6.3.12.2 MCU Domain
          1.        84
          2.        85
      14. 6.3.13 MCAN
        1. 6.3.13.1 MAIN Domain
          1.        88
          2.        89
      15. 6.3.14 MCSPI
        1. 6.3.14.1 MAIN Domain
          1.        92
          2.        93
          3.        94
          4.        95
          5.        96
        2. 6.3.14.2 MCU Domain
          1.        98
          2.        99
      16. 6.3.15 MDIO
        1. 6.3.15.1 MAIN Domain
          1.        102
      17. 6.3.16 MMC
        1. 6.3.16.1 MAIN Domain
          1.        105
          2.        106
      18. 6.3.17 OSPI
        1. 6.3.17.1 MAIN Domain
          1.        109
      19. 6.3.18 Power Supply
        1.       111
      20. 6.3.19 PRU_ICSSG
        1. 6.3.19.1 MAIN Domain
          1.        114
          2.        115
      21. 6.3.20 Reserved
        1.       117
      22. 6.3.21 SERDES
        1. 6.3.21.1 MAIN Domain
          1.        120
      23. 6.3.22 System and Miscellaneous
        1. 6.3.22.1 Boot Mode Configuration
          1. 6.3.22.1.1 MAIN Domain
            1.         124
        2. 6.3.22.2 Clock
          1. 6.3.22.2.1 MCU Domain
            1.         127
        3. 6.3.22.3 System
          1. 6.3.22.3.1 MAIN Domain
            1.         130
          2. 6.3.22.3.2 MCU Domain
            1.         132
        4. 6.3.22.4 VMON
          1.        134
      24. 6.3.23 TIMER
        1. 6.3.23.1 MAIN Domain
          1.        137
        2. 6.3.23.2 MCU Domain
          1.        139
      25. 6.3.24 UART
        1. 6.3.24.1 MAIN Domain
          1.        142
          2.        143
          3.        144
          4.        145
          5.        146
          6.        147
          7.        148
        2. 6.3.24.2 MCU Domain
          1.        150
          2.        151
      26. 6.3.25 USB
        1. 6.3.25.1 MAIN Domain
          1.        154
    4. 6.4 Pin Connectivity Requirements
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 7.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 7.7.4  eMMCPHY Electrical Characteristics
      5. 7.7.5  SDIO Electrical Characteristics
      6. 7.7.6  LVCMOS Electrical Characteristics
      7. 7.7.7  ADC12B Electrical Characteristics
      8. 7.7.8  USB2PHY Electrical Characteristics
      9. 7.7.9  SerDes PHY Electrical Characteristics
      10. 7.7.10 DDR Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Requirements
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Power Supply Sequencing
          1. 7.10.2.2.1 Power-Up Sequencing
          2. 7.10.2.2.2 Power-Down Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input Clocks / Oscillators
          1. 7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 7.10.5 Peripherals
        1. 7.10.5.1  CPSW3G
          1. 7.10.5.1.1 CPSW3G MDIO Timing
          2. 7.10.5.1.2 CPSW3G RMII Timing
          3. 7.10.5.1.3 CPSW3G RGMII Timing
          4. 7.10.5.1.4 CPSW3G IOSETs
        2. 7.10.5.2  DDRSS
        3. 7.10.5.3  ECAP
        4. 7.10.5.4  EPWM
        5. 7.10.5.5  EQEP
        6. 7.10.5.6  FSI
        7. 7.10.5.7  GPIO
        8. 7.10.5.8  GPMC
          1. 7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 7.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 7.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 7.10.5.8.4 GPMC0 IOSETs
        9. 7.10.5.9  I2C
        10. 7.10.5.10 MCAN
        11. 7.10.5.11 MCSPI
          1. 7.10.5.11.1 MCSPI — Controller Mode
          2. 7.10.5.11.2 MCSPI — Peripheral Mode
        12. 7.10.5.12 MMCSD
          1. 7.10.5.12.1 MMC0 - eMMC Interface
            1. 7.10.5.12.1.1 Legacy SDR Mode
            2. 7.10.5.12.1.2 High Speed SDR Mode
            3. 7.10.5.12.1.3 High Speed DDR Mode
            4. 7.10.5.12.1.4 HS200 Mode
          2. 7.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 7.10.5.12.2.1 Default Speed Mode
            2. 7.10.5.12.2.2 High Speed Mode
            3. 7.10.5.12.2.3 UHS–I SDR12 Mode
            4. 7.10.5.12.2.4 UHS–I SDR25 Mode
            5. 7.10.5.12.2.5 UHS–I SDR50 Mode
            6. 7.10.5.12.2.6 UHS–I DDR50 Mode
            7. 7.10.5.12.2.7 UHS–I SDR104 Mode
        13. 7.10.5.13 CPTS
        14. 7.10.5.14 OSPI
          1. 7.10.5.14.1 OSPI0 PHY Mode
            1. 7.10.5.14.1.1 OSPI0 With PHY Data Training
            2. 7.10.5.14.1.2 OSPI0 Without Data Training
              1. 7.10.5.14.1.2.1 OSPI0 PHY SDR Timing
              2. 7.10.5.14.1.2.2 OSPI0 PHY DDR Timing
          2. 7.10.5.14.2 OSPI0 Tap Mode
            1. 7.10.5.14.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.14.2.2 OSPI0 Tap DDR Timing
        15. 7.10.5.15 PCIe
        16. 7.10.5.16 PRU_ICSSG
          1. 7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 7.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 7.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 7.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 7.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 7.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 7.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 7.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 7.10.5.17 Timers
        18. 7.10.5.18 UART
        19. 7.10.5.19 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A53 Subsystem
      2. 8.2.2 Arm Cortex-R5F Subsystem (R5FSS)
      3. 8.2.3 Arm Cortex-M4F (M4FSS)
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 8.4 Other Subsystems
      1. 8.4.1 PDMA Controller
      2. 8.4.2 Peripherals
        1. 8.4.2.1  ADC
        2. 8.4.2.2  DCC
        3. 8.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 8.4.2.4  ECAP
        5. 8.4.2.5  EPWM
        6. 8.4.2.6  ELM
        7. 8.4.2.7  ESM
        8. 8.4.2.8  GPIO
        9. 8.4.2.9  EQEP
        10. 8.4.2.10 General-Purpose Memory Controller (GPMC)
        11. 8.4.2.11 I2C
        12. 8.4.2.12 MCAN
        13. 8.4.2.13 MCRC Controller
        14. 8.4.2.14 MCSPI
        15. 8.4.2.15 MMCSD
        16. 8.4.2.16 OSPI
        17. 8.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 8.4.2.18 Serializer/Deserializer (SerDes) PHY
        19. 8.4.2.19 Real Time Interrupt (RTI/WWDT)
        20. 8.4.2.20 Dual Mode Timer (DMTIMER)
        21. 8.4.2.21 UART
        22. 8.4.2.22 Universal Serial Bus Subsystem (USBSS)
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply
        1. 9.1.1.1 Power Supply Designs
        2. 9.1.1.2 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG, EMU, and TRACE
      4. 9.1.4 Unused Pins
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 DDR Board Design and Layout Guidelines
      2. 9.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal SPI devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 Thermal Solution Guidance
    3. 9.3 Clock Routing Guidelines
      1. 9.3.1 Oscillator Routing
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Table 6-59 PRU_ICSSG0 Signal Descriptions
SIGNAL NAME [1]PIN TYPE [2]DESCRIPTION [3]ALV PIN [4]
PRG0_ECAP0_IN_APWM_OUTIOPRU-ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) OutputR2, U5
PRG0_ECAP0_SYNC_INIPRU-ICSSG ECAP Sync Input P5, V5
PRG0_ECAP0_SYNC_OUTOPRU-ICSSG ECAP Sync OutputAA4, V5
PRG0_IEP0_EDIO_OUTVALIDOPRU_ICSSG Industrial Ethernet Digital I/O OutvalidC13
PRG0_IEP0_EDC_LATCH_IN0IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputV1
PRG0_IEP0_EDC_LATCH_IN1IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputT1
PRG0_IEP0_EDC_SYNC_OUT0OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputW1
PRG0_IEP0_EDC_SYNC_OUT1OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputU1
PRG0_IEP0_EDIO_DATA_IN_OUT28IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputW6
PRG0_IEP0_EDIO_DATA_IN_OUT29IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputAA5
PRG0_IEP0_EDIO_DATA_IN_OUT30IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputY5
PRG0_IEP0_EDIO_DATA_IN_OUT31IOPRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputV6
PRG0_IEP1_EDC_LATCH_IN0IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputP5
PRG0_IEP1_EDC_LATCH_IN1IPRU_ICSSG Industrial Ethernet Distributed Clock Latch InputW5
PRG0_IEP1_EDC_SYNC_OUT0OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputR2
PRG0_IEP1_EDC_SYNC_OUT1OPRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputV5
PRG0_MDIO0_MDCOPRU-ICSSG MDIO ClockP3
PRG0_MDIO0_MDIOIOPRU-ICSSG MDIO DataP2
PRG0_PRU0_GPI0IPRU-ICSSG PRU Data InputY1
PRG0_PRU0_GPI1IPRU-ICSSG PRU Data InputR4
PRG0_PRU0_GPI2IPRU-ICSSG PRU Data InputU2
PRG0_PRU0_GPI3IPRU-ICSSG PRU Data InputV2
PRG0_PRU0_GPI4IPRU-ICSSG PRU Data InputAA2
PRG0_PRU0_GPI5IPRU-ICSSG PRU Data InputR3
PRG0_PRU0_GPI6IPRU-ICSSG PRU Data InputT3
PRG0_PRU0_GPI7IPRU-ICSSG PRU Data InputT1
PRG0_PRU0_GPI8IPRU-ICSSG PRU Data InputT2
PRG0_PRU0_GPI9IPRU-ICSSG PRU Data InputW6
PRG0_PRU0_GPI10IPRU-ICSSG PRU Data InputAA5
PRG0_PRU0_GPI11IPRU-ICSSG PRU Data InputY3
PRG0_PRU0_GPI12IPRU-ICSSG PRU Data InputAA3
PRG0_PRU0_GPI13IPRU-ICSSG PRU Data InputR6
PRG0_PRU0_GPI14IPRU-ICSSG PRU Data InputV4
PRG0_PRU0_GPI15IPRU-ICSSG PRU Data InputT5
PRG0_PRU0_GPI16IPRU-ICSSG PRU Data InputU4
PRG0_PRU0_GPI17IPRU-ICSSG PRU Data InputU1
PRG0_PRU0_GPI18IPRU-ICSSG PRU Data InputV1
PRG0_PRU0_GPI19IPRU-ICSSG PRU Data InputW1
PRG0_PRU0_GPO0IOPRU-ICSSG PRU Data OutputY1
PRG0_PRU0_GPO1IOPRU-ICSSG PRU Data OutputR4
PRG0_PRU0_GPO2IOPRU-ICSSG PRU Data OutputU2
PRG0_PRU0_GPO3IOPRU-ICSSG PRU Data OutputV2
PRG0_PRU0_GPO4IOPRU-ICSSG PRU Data OutputAA2
PRG0_PRU0_GPO5IOPRU-ICSSG PRU Data OutputR3
PRG0_PRU0_GPO6IOPRU-ICSSG PRU Data OutputT3
PRG0_PRU0_GPO7IOPRU-ICSSG PRU Data OutputT1
PRG0_PRU0_GPO8IOPRU-ICSSG PRU Data OutputT2
PRG0_PRU0_GPO9IOPRU-ICSSG PRU Data OutputW6
PRG0_PRU0_GPO10IOPRU-ICSSG PRU Data OutputAA5
PRG0_PRU0_GPO11IOPRU-ICSSG PRU Data OutputY3
PRG0_PRU0_GPO12IOPRU-ICSSG PRU Data OutputAA3
PRG0_PRU0_GPO13IOPRU-ICSSG PRU Data OutputR6
PRG0_PRU0_GPO14IOPRU-ICSSG PRU Data OutputV4
PRG0_PRU0_GPO15IOPRU-ICSSG PRU Data OutputT5
PRG0_PRU0_GPO16IOPRU-ICSSG PRU Data OutputU4
PRG0_PRU0_GPO17IOPRU-ICSSG PRU Data OutputU1
PRG0_PRU0_GPO18IOPRU-ICSSG PRU Data OutputV1
PRG0_PRU0_GPO19IOPRU-ICSSG PRU Data OutputW1
PRG0_PRU1_GPI0IPRU-ICSSG PRU Data InputY2
PRG0_PRU1_GPI1IPRU-ICSSG PRU Data InputW2
PRG0_PRU1_GPI2IPRU-ICSSG PRU Data InputV3
PRG0_PRU1_GPI3IPRU-ICSSG PRU Data InputT4
PRG0_PRU1_GPI4IPRU-ICSSG PRU Data InputW3
PRG0_PRU1_GPI5IPRU-ICSSG PRU Data InputP4
PRG0_PRU1_GPI6IPRU-ICSSG PRU Data InputR5
PRG0_PRU1_GPI7IPRU-ICSSG PRU Data InputW5
PRG0_PRU1_GPI8IPRU-ICSSG PRU Data InputR1
PRG0_PRU1_GPI9IPRU-ICSSG PRU Data InputY5
PRG0_PRU1_GPI10IPRU-ICSSG PRU Data InputV6
PRG0_PRU1_GPI11IPRU-ICSSG PRU Data InputW4
PRG0_PRU1_GPI12IPRU-ICSSG PRU Data InputY4
PRG0_PRU1_GPI13IPRU-ICSSG PRU Data InputT6
PRG0_PRU1_GPI14IPRU-ICSSG PRU Data InputU6
PRG0_PRU1_GPI15IPRU-ICSSG PRU Data InputU5
PRG0_PRU1_GPI16IPRU-ICSSG PRU Data InputAA4
PRG0_PRU1_GPI17IPRU-ICSSG PRU Data InputV5
PRG0_PRU1_GPI18IPRU-ICSSG PRU Data InputP5
PRG0_PRU1_GPI19IPRU-ICSSG PRU Data InputR2
PRG0_PRU1_GPO0IOPRU-ICSSG PRU Data OutputY2
PRG0_PRU1_GPO1IOPRU-ICSSG PRU Data OutputW2
PRG0_PRU1_GPO2IOPRU-ICSSG PRU Data OutputV3
PRG0_PRU1_GPO3IOPRU-ICSSG PRU Data OutputT4
PRG0_PRU1_GPO4IOPRU-ICSSG PRU Data OutputW3
PRG0_PRU1_GPO5IOPRU-ICSSG PRU Data OutputP4
PRG0_PRU1_GPO6IOPRU-ICSSG PRU Data OutputR5
PRG0_PRU1_GPO7IOPRU-ICSSG PRU Data OutputW5
PRG0_PRU1_GPO8IOPRU-ICSSG PRU Data OutputR1
PRG0_PRU1_GPO9IOPRU-ICSSG PRU Data OutputY5
PRG0_PRU1_GPO10IOPRU-ICSSG PRU Data OutputV6
PRG0_PRU1_GPO11IOPRU-ICSSG PRU Data OutputW4
PRG0_PRU1_GPO12IOPRU-ICSSG PRU Data OutputY4
PRG0_PRU1_GPO13IOPRU-ICSSG PRU Data OutputT6
PRG0_PRU1_GPO14IOPRU-ICSSG PRU Data OutputU6
PRG0_PRU1_GPO15IOPRU-ICSSG PRU Data OutputU5
PRG0_PRU1_GPO16IOPRU-ICSSG PRU Data OutputAA4
PRG0_PRU1_GPO17IOPRU-ICSSG PRU Data OutputV5
PRG0_PRU1_GPO18IOPRU-ICSSG PRU Data OutputP5
PRG0_PRU1_GPO19IOPRU-ICSSG PRU Data OutputR2
PRG0_PWM0_TZ_INIPRU_ICSSG PWM Trip Zone InputV1
PRG0_PWM0_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputW1
PRG0_PWM1_TZ_INIPRU_ICSSG PWM Trip Zone InputP5
PRG0_PWM1_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputR2
PRG0_PWM2_TZ_INIPRU_ICSSG PWM Trip Zone InputT18, V6
PRG0_PWM2_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputR1, U21
PRG0_PWM3_TZ_INIPRU_ICSSG PWM Trip Zone InputP16, W6
PRG0_PWM3_TZ_OUTOPRU_ICSSG PWM Trip Zone OutputR17, Y3
PRG0_PWM0_A0IOPRU_ICSSG PWM Output AAA3
PRG0_PWM0_A1IOPRU_ICSSG PWM Output AV4
PRG0_PWM0_A2IOPRU_ICSSG PWM Output AU4
PRG0_PWM0_B0IOPRU_ICSSG PWM Output BR6
PRG0_PWM0_B1IOPRU_ICSSG PWM Output BT5
PRG0_PWM0_B2IOPRU_ICSSG PWM Output BU1
PRG0_PWM1_A0IOPRU_ICSSG PWM Output AY4
PRG0_PWM1_A1IOPRU_ICSSG PWM Output AU6
PRG0_PWM1_A2IOPRU_ICSSG PWM Output AAA4
PRG0_PWM1_B0IOPRU_ICSSG PWM Output BT6
PRG0_PWM1_B1IOPRU_ICSSG PWM Output BU5
PRG0_PWM1_B2IOPRU_ICSSG PWM Output BV5
PRG0_PWM2_A0IOPRU_ICSSG PWM Output AU2, U20
PRG0_PWM2_A1IOPRU_ICSSG PWM Output AT2, U19
PRG0_PWM2_A2IOPRU_ICSSG PWM Output AV19, V3
PRG0_PWM2_B0IOPRU_ICSSG PWM Output BAA2, U18
PRG0_PWM2_B1IOPRU_ICSSG PWM Output BAA5, V20
PRG0_PWM2_B2IOPRU_ICSSG PWM Output BT17, W3
PRG0_PWM3_A0IOPRU_ICSSG PWM Output AV18, Y1
PRG0_PWM3_A1IOPRU_ICSSG PWM Output AR18, T3
PRG0_PWM3_A2IOPRU_ICSSG PWM Output AT19, V2
PRG0_PWM3_B0IOPRU_ICSSG PWM Output BR4, Y21
PRG0_PWM3_B1IOPRU_ICSSG PWM Output BT1, T21
PRG0_PWM3_B2IOPRU_ICSSG PWM Output BR3, W19
PRG0_RGMII1_RXCIPRU_ICSSG RGMII Receive ClockT3
PRG0_RGMII1_RX_CTLIPRU_ICSSG RGMII Receive ControlAA2
PRG0_RGMII1_TXCIOPRU_ICSSG RGMII Transmit ClockU4
PRG0_RGMII1_TX_CTLOPRU_ICSSG RGMII Transmit ControlT5
PRG0_RGMII2_RXCIPRU_ICSSG RGMII Receive ClockR5
PRG0_RGMII2_RX_CTLIPRU_ICSSG RGMII Receive ControlW3
PRG0_RGMII2_TXCIOPRU_ICSSG RGMII Transmit ClockAA4
PRG0_RGMII2_TX_CTLOPRU_ICSSG RGMII Transmit ControlU5
PRG0_RGMII1_RD0IPRU_ICSSG RGMII Receive DataY1
PRG0_RGMII1_RD1IPRU_ICSSG RGMII Receive DataR4
PRG0_RGMII1_RD2IPRU_ICSSG RGMII Receive DataU2
PRG0_RGMII1_RD3IPRU_ICSSG RGMII Receive DataV2
PRG0_RGMII1_TD0OPRU_ICSSG RGMII Transmit DataY3
PRG0_RGMII1_TD1OPRU_ICSSG RGMII Transmit DataAA3
PRG0_RGMII1_TD2OPRU_ICSSG RGMII Transmit DataR6
PRG0_RGMII1_TD3OPRU_ICSSG RGMII Transmit DataV4
PRG0_RGMII2_RD0IPRU_ICSSG RGMII Receive DataY2
PRG0_RGMII2_RD1IPRU_ICSSG RGMII Receive DataW2
PRG0_RGMII2_RD2IPRU_ICSSG RGMII Receive DataV3
PRG0_RGMII2_RD3IPRU_ICSSG RGMII Receive DataT4
PRG0_RGMII2_TD0OPRU_ICSSG RGMII Transmit DataW4
PRG0_RGMII2_TD1OPRU_ICSSG RGMII Transmit DataY4
PRG0_RGMII2_TD2OPRU_ICSSG RGMII Transmit DataT6
PRG0_RGMII2_TD3OPRU_ICSSG RGMII Transmit DataU6
PRG0_UART0_CTSnIPRU-ICSSG UART Clear to Send (active low)W6
PRG0_UART0_RTSnOPRU-ICSSG UART Request to Send (active low)AA5
PRG0_UART0_RXDIPRU-ICSSG UART Receive DataY5
PRG0_UART0_TXDOPRU-ICSSG UART Transmit DataV6