8.3.4 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A differential input of 50 mV produces a stream of ones and zeros that are high 89.06% of the time. With 16 bits of resolution on the decimation filter, that percentage ideally corresponds to code 58368. A differential input of –50 mV produces a stream of ones and zeros that are high 10.94% of the time and ideally results in code 7168 with a 16-bit resolution decimation filter. This –50-mV to 50-mV input voltage range is also the specified linear range FSR of the AMC1106 with performance as specified in this document. If the input voltage value exceeds this range, the output of the modulator shows nonlinear behavior where the quantization noise increases. The output of the modulator clips with a stream of only zeros with an input less than or equal to –64 mV or with a stream of only ones with an input greater than or equal to 64 mV. In this case, however, the AMC1106 generates a single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see theFail-Safe Output section for more details). Figure 45 shows the input voltage versus the modulator output signal.

Figure 45. Analog Input versus AMC1106 Modulator Output

Equation 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception of a full-scale input signal, as described in theOutput Behavior in Case of a Full-Scale Input section):

Equation 1.

The AMC1106 system clock is provided externally at the CLKIN pin. For more details, see the Switching Characteristics table and the Manchester Coding Feature section.