SBAS512F April   2011  – February 2020 AMC1204

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Device Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Timing Requirements
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Digital Output
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Digital Filter Usage
    2. 8.2 Typical Application
      1. 8.2.1 Frequency Inverter Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Example of a Resolver-Based Motor Control Analog Front End
      3. 8.2.3 Isolated Voltage Sensing
        1. 8.2.3.1 Design Requirements
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.1 Digital Filter Usage

The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, built with minimal effort and hardware, is a sinc3-type filter, as shown in Equation 1:

Equation 1. AMC1204 q_hz_sinc3_bas512.gif

This filter provides the best output performance at the lowest hardware size (count of digital gates). For an oversampling rate (OSR) in the range of 16 to 256, this filter is a good choice. All the characterization in this document is also done with a sinc3 filter with OSR = 256 and an output word width of 16 bits.

In a sinc3 filter response (shown in Figure 48 and Figure 49), the location of the first notch occurs at the frequency of output data rate fDATA = fCLK/OSR. The –3-dB point is located at half the Nyquist frequency or fDATA/4. For some applications, it may be necessary to use another filter type with different frequency response. Performance can be improved, for example, by using a cascaded filter structure. The first decimation stage could be built of a sinc3 filter with a low OSR and the second stage using a high-order filter.

AMC1204 ai_frq_resp_sinc3_bas512.gif
Figure 48. Frequency Response Of The Sinc3 Filter
AMC1204 ai_pole_resp_sinc3_bas512.gif
Figure 49. Pole Response Of The Sinc3 Filter

The effective number of bits (ENOB) is often used to compare the performance of ADCs and ΔΣ modulators. Figure 51 illustrates the ENOB of the AMC1204 and AMC1204B with different oversampling ratios. In this data sheet, this number is calculated from SNR using Equation 2:

Equation 2. AMC1204 q_snr_bas512.gif

An example code for an implementation of a sinc3 filter in an FPGA follows. For more information, see the Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for download at www.ti.com.

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FLT is port(RESN, MOUT, MCLK, CNR : in std_logic; CN5 : out std_logic_vector(23 downto 0)); end FLT; architecture RTL of FLT is signal DN0, DN1, DN3, DN5 : std_logic_vector(23 downto 0); signal CN1, CN2, CN3, CN4 : std_logic_vector(23 downto 0); signal DELTA1 : std_logic_vector(23 downto 0); begin process(MCLK, RESn) begin if RESn = '0' then DELTA1 <= (others => '0'); elsif MCLK'event and MCLK = '1' then if MOUT = '1' then DELTA1 <= DELTA1 + 1; end if; end if; end process; process(RESN, MCLK) begin if RESN = '0' then CN1 <= (others => '0'); CN2 <= (others => '0'); elsif MCLK'event and MCLK = '1' then CN1 <= CN1 + DELTA1; CN2 <= CN2 + CN1; end if; end process; process(RESN, CNR) begin if RESN = '0' then DN0 <= (others => '0'); DN1 <= (others => '0'); DN3 <= (others => '0'); DN5 <= (others => '0'); elsif CNR'event and CNR = '1' then DN0 <= CN2; DN1 <= DN0; DN3 <= CN3; DN5 <= CN4; end if; end process; CN3 <= DN0 - DN1; CN4 <= CN3 - DN3; CN5 <= CN4 - DN5; end RTL;