SBAS654G June 2014 – January 2020 AMC1305L25 , AMC1305M05 , AMC1305M25
PRODUCTION DATA.
| PARAMETER | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|
| tCLK | CLKIN, CLKIN_N clock period | 49.75 | 50 | 200 | ns |
| tHIGH | CLKIN, CLKIN_N clock high time | 19.9 | 25 | 120 | ns |
| tLOW | CLKIN, CLKIN_N clock low time | 19.9 | 25 | 120 | ns |
| tD | Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay,
CLOAD = 5 pF |
0 | 15 | ns | |
| tISTART | Interface startup time
(DVDD at 3.0 V min to DOUT, DOUT_N valid with AVDD ≥ 4.5 V) |
32 | 32 | CLKIN cycles | |
| tASTART | Analog startup time (AVDD step up to 4.5 V with DVDD ≥ 3.0 V) | 1 | ms | ||
Figure 1. Digital Interface Timing
Figure 2. Digital Interface Startup Timing