SLAS836 March   2014 AMC7832

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Power Amp Biasing Diagram
  5. 5 Revision History
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements - Serial Interface
    7. 7.7  Typical Characteristics: DAC
    8. 7.8  Typical Characteristics: ADC
    9. 7.9  Typical Characteristics: Reference
    10. 7.10 Typical Characteristics: Temperature Sensor
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converters (DACs)
        1. 8.3.1.1 DAC Output Range and Clamp Configuration
        2. 8.3.1.2 DAC Register Structure
        3. 8.3.1.3 DAC Clear Operation
      2. 8.3.2 Analog-to-Digital Converter (ADC)
        1. 8.3.2.1 Analog Inputs
          1. 8.3.2.1.1 Bipolar Analog Inputs
          2. 8.3.2.1.2 Unipolar Analog Inputs
        2. 8.3.2.2 ADC Sequencing
        3. 8.3.2.3 ADC Synchronization
        4. 8.3.2.4 Programmable Out-of-Range Alarms
          1. 8.3.2.4.1 Unipolar Inputs Out-of-Range Alarms
          2. 8.3.2.4.2 Internal Temperature Sensor Out-of-Range Alarms
          3. 8.3.2.4.3 ALARMIN Alarm
          4. 8.3.2.4.4 Hysteresis
          5. 8.3.2.4.5 False-Alarm Protection
      3. 8.3.3 Internal Temperature Sensor
      4. 8.3.4 Internal Reference
      5. 8.3.5 General Purpose I/Os
    4. 8.4 Programming
    5. 8.5 Register Map
      1. 8.5.1  Interface Configuration: Address 0x00 - 0x02
      2. 8.5.2  Device Identification: Address 0x03 - 0x0D
      3. 8.5.3  Register Update (Buffered Registers): Address 0x0F
      4. 8.5.4  General Device Configuration: Address 0x10 - 0x17
      5. 8.5.5  DAC Clear And ALARMOUT Source Select: Address 0x1A - 0x1D
      6. 8.5.6  DAC Range: Address 0x1E
      7. 8.5.7  ADC Data: Address 0x20 - 0x41
      8. 8.5.8  DAC Data: Address 0x50 - 0x67
      9. 8.5.9  Status Registers: Address 0x70 - 0x72
      10. 8.5.10 Temperature And GPIO Data: Address 0x78 - 0x7A
      11. 8.5.11 Out-Of-Range ADC Thresholds: Address 0x80 - 0x93
      12. 8.5.12 Hysteresis: Address 0xA0 - 0xA5
      13. 8.5.13 Power-Down Registers: Address 0xB0 - 0xB3
      14. 8.5.14 ADC Trigger: Address 0xC0
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application Schematic
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 ADC Input Conditioning
        2. 9.2.3.2 DAC Output Range Selection
        3. 9.2.3.3 Temperature Sensing Applications
        4. 9.2.3.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

The preferred (not required) order for applying power is IOVDD, DVDD/AVDD and then AVCC/AVEE. When power sequencing, ensure that all digital terminals are not powered, or in an active state while IOVDD ramps. This can be accomplished by attaching 10-kΩ pull-up resistors to IOVDD, or pull-down resistors to DGND.

The supply voltage ranges are specified in the Recommended Operating Conditions but are repeated here for convenience.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE RANGE
AVDD 4.5 5 5.5 V
DVDD DVDD must be equal to AVDD 4.5 5 5.5 V
IOVDD IOVDD must be equal or less than DVDD 1.8 5.5 V
AVCC 4.5 12 12.5 V
AVEE –12.5 –12 0 V
AVSSA,B,C,D AVEE 0 V
OPERATING RANGE
Specified temperature range –40 25 105 °C

All registers initialize to the default values after these supplies have been established. Communication with the AMC7832 will be valid after a 250-µS maximum power-on reset delay. The default state of all analog blocks is off as determined by the power-down registers (0xB2 and 0xB3). Before writing to this register, a hardware reset should be issued to ensure specified operation of the AMC7832. Communication to the AMC7832 will be valid after a maximum 250-µS reset delay from the rising edge of RESET.

If DVDD falls below +4.5-V, the minimum supply value of DVDD, either a hardware or power-on reset should be issued before proper operation can be resumed.

When powered on, the internal POR circuit invokes a power-on reset, which performs the equivalent function of the RESET terminal. To ensure a POR, DVDD must start from a level below 750-mV.