SWRS236C March   2021  – January 2024 AWR1843AOP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Pin Functions - Digital and Analog [ALP Package]
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Supply Specifications
    6. 6.6  Power Consumption Summary
    7. 6.7  RF Specification
    8. 6.8  CPU Specifications
    9. 6.9  Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1  Antenna Radiation Patterns
        1. 6.10.1.1 Antenna Radiation Patterns for Receiver
        2. 6.10.1.2 Antenna Radiation Patterns for Transmitter
      2. 6.10.2  Antenna Positions
      3. 6.10.3  Power Supply Sequencing and Reset Timing
      4. 6.10.4  Input Clocks and Oscillators
        1. 6.10.4.1 Clock Specifications
      5. 6.10.5  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 6.10.5.1 Peripheral Description
        2. 6.10.5.2 MibSPI Transmit and Receive RAM Organization
          1. 6.10.5.2.1 SPI Timing Conditions
          2. 6.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 6.10.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 6.10.5.3 SPI Peripheral Mode I/O Timings
          1. 6.10.5.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 6.10.5.4 Typical Interface Protocol Diagram (Slave Mode)
      6. 6.10.6  LVDS Interface Configuration
        1. 6.10.6.1 LVDS Interface Timings
      7. 6.10.7  General-Purpose Input/Output
        1. 6.10.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-4685AB93-A014-47EA-9F05-952FFC28DBFA/T4362547-45 #GUID-4685AB93-A014-47EA-9F05-952FFC28DBFA/T4362547-50
      8. 6.10.8  Controller Area Network Interface (DCAN)
        1. 6.10.8.1 Dynamic Characteristics for the DCANx TX and RX Pins
      9. 6.10.9  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 6.10.9.1 Dynamic Characteristics for the CANx TX and RX Pins
      10. 6.10.10 Serial Communication Interface (SCI)
        1. 6.10.10.1 SCI Timing Requirements
      11. 6.10.11 Inter-Integrated Circuit Interface (I2C)
        1. 6.10.11.1 I2C Timing Requirements #GUID-64613E7E-5DDF-4B01-8FA0-13739060F368/T4362547-185
      12. 6.10.12 Quad Serial Peripheral Interface (QSPI)
        1. 6.10.12.1 QSPI Timing Conditions
        2. 6.10.12.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6A95C194-2C40-46FE-9793-4574200DA2C4/T4362547-210 #GUID-6A95C194-2C40-46FE-9793-4574200DA2C4/T4362547-209
        3. 6.10.12.3 QSPI Switching Characteristics
      13. 6.10.13 ETM Trace Interface
        1. 6.10.13.1 ETMTRACE Timing Conditions
        2. 6.10.13.2 ETM TRACE Switching Characteristics
      14. 6.10.14 Data Modification Module (DMM)
        1. 6.10.14.1 DMM Timing Requirements
      15. 6.10.15 JTAG Interface
        1. 6.10.15.1 JTAG Timing Conditions
        2. 6.10.15.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 6.10.15.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Subsystems
      1. 7.3.1 RF and Analog Subsystem
        1. 7.3.1.1 Clock Subsystem
        2. 7.3.1.2 Transmit Subsystem
        3. 7.3.1.3 Receive Subsystem
      2. 7.3.2 Processor Subsystem
      3. 7.3.3 Automotive Interface
      4. 7.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 7.3.5 DSP Subsystem Memory Map
    4. 7.4 Other Subsystems
      1. 7.4.1 ADC Channels (Service) for User Application
        1. 7.4.1.1 GP-ADC Parameter
  9. 8 Monitoring and Diagnostics
    1. 8.1 Monitoring and Diagnostic Mechanisms
      1. 8.1.1 Error Signaling Module
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Reference Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALP|180
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 DSP Subsystem Memory Map

Table 7-2 shows the DSP C674x memory map.

Table 7-2 DSP C674x Memory Map
NameFrame Address (Hex)SizeDescription
StartEnd
DSP Memories
DSP_L1D0x00F0_00000x00F0_7FFF32 KiBL1 data memory space
DSP_L1P0x00E0_00000x00E0_7FFF32 KiBL1 program memory space
DSP_L2_UMAP00x0080_00000x0081_FFFF128 KiBL2 RAM space
DSP_L2_UMAP10x007E_00000x007F_FFFF128 KiBL2 RAM space
EDMA
TPCC00x0201_00000x0201_3FFF16 KiBTPCC0 module configuration space
TPCC10x020A_00000x020A_3FFF16 KiBTPCC1 module configuration space
TPTC00x0200 00000x0200 03FF1 KiBTPTC0 module configuration space
TPTC10x0200 08000x0200 0BFF1 KiBTPTC1 module configuration space
TPTC20x0209_00000x0209_03FF1 KiBTPTC2 module configuration space
TPTC30x0209_04000x0209_07FF1 KiBTPTC3 module configuration space
Control Registers
DSS_REG0x0200_04000x0200_07FF864 BDSPSS control module registers
DSS_REG20x0200_0C000x0200_0FFF624 BDSPSS control module registers
System Memories
ADC Buffer0x2100_00000x2100_7FFC32 KiBADC buffer memory space
CBUFF-FIFO0x2102_00000x2102_3FFC16 KiBCommon buffer FIFO space
L3-Shared memory0x2000_00000x201F_FFFF2 MBL3 shared memory space
HS-RAM0x2108_00000x2108_7FFC32 KiBHandshake memory space
System Peripherals
RTI-A/WD0x0202_00000x0202_00FF192 BRTI-A module configuration registers
RTI-B0x020F_00000x020F_00FF192 BRTI-B module configuration registers
CBUFF0x0207_00000x0207_03FF564 BCommon Buffer module Configuration registers
Mail Box
MSS<->RADARSS		0x5060_10000x5060_17FF2 KiBRADARSS to MSS mailbox memory space
0x5060_20000x5060_27FFMSS to RADARSS mailbox memory space
0x0460_80000x0460_80FF188 BMSS to RADARSS mailbox Configuration registers
0x0460_80600x0460_86FFRADARSS to MSS mailbox Configuration registers
Mail Box
MSS<->DSPSS		0x5060_40000x5060_47FF2 KiBDSPSS to MSS mailbox memory space
0x5060_50000x5060_57FFMSS to DSPSS mailbox memory space
0x0460_84000x0460_84FF188 BMSS to DSPSS mailbox Configuration registers
0x0460_83000x0460_83FFDSPSS to MSS mailbox Configuration registers
Mail Box
RADARSS<->DSPSS		0x5060_60000x5060_67FF2 KiBRADARSS to DSPSS mailbox memory space
0x5060_70000x5060_7FFFDSPSS to RADARSS mailbox memory space
0x0460_82000x0460_82FF188 BRADARSS to DSPSS mailbox Configuration registers
0x0460_81000x0460_81FFDSPSS to RADARSS mailbox Configuration registers
Safety Modules
ESM0x020D_000092 BESM module Configuration registers
CRC0x2200_00000x2200_03FF1 KiBCRC module Configuration registers
STC0x0204_00000x0204_01FF284 BSTC module Configuration registers
Nonsystem Peripherals
SCI0x0203_00000x0203_00FF148 BSCI module Configuration registers