SWRS273A november   2021  – march 2023 AWR2944

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Pin Configurations and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions - Digital
    4. 6.4 Signal Descriptions - Analog
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
    7. 7.7  Power Consumption Summary
    8. 7.8  RF Specifications
    9. 7.9  Thermal Resistance Characteristics
    10. 7.10 Power Supply Sequencing and Reset Timing
    11. 7.11 Input Clocks and Oscillators
      1. 7.11.1 Clock Specifications
    12. 7.12 Peripheral Information
      1. 7.12.1  QSPI Flash Memory Peripheral
        1. 7.12.1.1 QSPI Timing Conditions
        2. 7.12.1.2 QSPI Timing Requirements #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 7.12.1.3 QSPI Switching Characteristics #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-64 #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-65
      2. 7.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.12.2.1 MibSPI Peripheral Description
        2. 7.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 7.12.2.2.1 SPI Timing Conditions
          2. 7.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-236 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-237 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-238
          3. 7.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-244 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-245 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-246
        3. 7.12.2.3 SPI Peripheral Mode I/O Timings
          1. 7.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-70 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-71 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-73
      3. 7.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 7.12.3.1  RGMII/MII Timing Conditions
        2. 7.12.3.2  RGMII Transmit Clock Switching Characteristics
        3. 7.12.3.3  RGMII Transmit Data and Control Switching Characteristics
        4. 7.12.3.4  RGMII Recieve Clock Timing Requirements
        5. 7.12.3.5  RGMII Receive Data and Control Timing Requirements
        6. 7.12.3.6  RMII Transmit Clock Switching Characteristics
        7. 7.12.3.7  RMII Transmit Data and Control Switching Characteristics
        8. 7.12.3.8  RMII Receive Clock Timing Requirements
        9. 7.12.3.9  RMII Receive Data and Control Timing Requirements
        10. 7.12.3.10 MII Transmit Switching Characteristics
        11. 7.12.3.11 MII Receive Clock Timing Requirements
        12. 7.12.3.12 MII Receive Timing Requirements
        13. 7.12.3.13 MII Transmit Clock Timing Requirements
        14. 7.12.3.14 MDIO Interface Timings
      4. 7.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 7.12.4.1 LVDS Interface Configuration
        2. 7.12.4.2 LVDS Interface Timings
      5. 7.12.5  UART Peripheral
        1. 7.12.5.1 SCI Timing Requirements
      6. 7.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 7.12.6.1 I2C Timing Requirements #GUID-437677C7-D935-4733-A64D-553EFECA73F7/T4362547-185
      7. 7.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 7.12.8  CSI2 Receiver Peripheral
        1. 7.12.8.1 CSI2 Switching Characteristics
      9. 7.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 7.12.10 General-Purpose Input/Output
        1. 7.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-45 #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-50
    13. 7.13 Emulation and Debug
      1. 7.13.1 Emulation and Debug Description
      2. 7.13.2 JTAG Interface
        1. 7.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 7.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 7.13.3 ETM Trace Interface
        1. 7.13.3.1 ETM TRACE Timing Requirements
        2. 7.13.3.2 ETM TRACE Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 RF Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Automotive Interfaces
    4. 8.4 Other Subsystems
      1. 8.4.1 Hardware Accelerator Subsystem
      2. 8.4.2 Security – Hardware Security Module
      3. 8.4.3 ADC Channels (Service) for User Application
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short and Medium Range Radar
    3. 10.3 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from November 10, 2021 to March 31, 2023 (from Revision * (November 2021) to Revision A (March 2023))

  • (Title): Updated the datasheet title from" AWR2944" to "AWR2943/44"Go
  • (Title): Updated the datasheet title from" AWR2944" to "AWR2943/44"Go
  • (Features) : Updated RX Noise Figure from 13 to 12 dB and TX Output power from 12 to 13.5 dBmGo
  • (Features) : Added Cortex R5F and DSP C66x maximum operating frequencyGo
  • (Features) : Updated version of HWA from 2.0 to 2.1Go
  • (Features) : Added recommendations on power management solutionsGo
  • (Description): Updated ES2.0 silicon orderable part numbers (OPNs). Go
  • (Functional Block Diagram) : Updated the diagram to remove a footnote. Go
  • (Signal Descriptions - Digital) : Corrected descriptions for MSS_RGMII_RDx pinsGo
  • (Signal Descriptions - Digital) : Added a table-note for usage of MSS_MIBSPIB signalsGo
  • (Signal Descriptions - Digital) : Removed pins F16 and E17 from TRACE_CLK and TRACE_CTLGo
  • (Signal Descriptions - Analog) : Added a table-note for TX4Go
  • (Recommended Operating Conditions) : Updated MAX values for 1.2V digital and SRAM supply; and 1.8V supplyGo
  • (VPP Specifications) - Warranty Impact : Rephrased sectionGo
  • (Power Supply Specification) : Added Supply Ripple specsGo
  • (Power Supply Specification) : Added recommendations on power management solutionsGo
  • (Power Consumption Summary) : Updated the Max peak current numbers for 1.2V and 1.8V respectively from 2100mA and 600mA to 2000mA and 550mA in Table - Maximum Current Ratings at Power Terminals for ES2.0 siliconGo
  • (Power Consumption Summary) : Updated the Description conditions and power numbers in Table - Average Power Consumption at Power Terminals for ES2.0 siliconGo
  • (RF Specifications) : Improved Typical Noise Figure from 13dB to 12dB in ES2.0 siliconGo
  • (RF Specifications) : Improved Typical Transmitter Output power from 12dBm to 13.5dBm in ES2.0 siliconGo
  • (RF Specifications) : Improved Typical 1-dB compression point (Out Of Band) from -11dBm to -10dBm in ES2.0 siliconGo
  • (RF Specifications) : Updated table-notes for 1-dB compression point (Out Of Band) measurement technique and a new note added for VCO2 rangeGo
  • (RF Specifications) : Updated Noise Figure, In-band P1dB vs Receiver Gain figure in the sectionGo
  • (Clock Specifications): Updated/Changed "Crystal Electrical Characteristics (Oscillator Mode)" to reflect correct device operating temperature rangeGo
  • (QSPI Timing Conditions) : Updated the Output load capacitance from 2pF to 5pFGo
  • Updated the 29xx ES1.0 spec : Number 13.2 in Q12 and Q14 changed to 7.3 from 13.2.Go
  • (QSPI Timing Requirements) : Updated the Setup time (Q12 and Q14) from 13.2ns to 5 nsGo
  • (QSPI Switching Characteristics): Updated/Changed Cycle time, sclk from 15ns to 12.5ns; Go
  • (QSPI Switching Characteristics): Updated/Changed Pulse duration, sclk i.e. [Q2, Q3] from 0.5*P – 1.5 to 0.5*P – 0.625 (Min). Go
  • (QSPI Switching Characteristics): Updated/Changed Delay time, sclk falling edge to d[0] transition i.e. [Q6, Q9] from 5.5ns to 2ns (Max) and -2.5ns to -4.5ns (Min). Go
  • (SPI Timing Conditions): Updated/Changed CLOAD, Output load capacitance from 15pF to 20pF (Max). Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =0 ): Updated/Changed Cycle time, SPICLK from 40ns to 20ns; Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =0): Updated/Changed Pulse duration, SPICLK i.e. [Q2, Q3] from 0.5tc(SPC)M +- 4 to 0.5tc(SPC)M +- 2(Min/Max). Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =0): Updated/Changed Delay time, SPISIMO valid before SPICLK low, i.e. [Q4] from 0.5tc(SPC)M – 14 to 0.5tc(SPC)M – 7 (Min). Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =0): Updated/Changed Valid time, SPISIMO data valid after SPICLK low, i.e. [Q5] from 0.5tc(SPC)M – 18 to 0.5tc(SPC)M – 8 (Min). Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =0): Updated/Changed Hold time, SPISOMI data valid after SPICLK i.e. [Q9] from 3ns to 2ns (Min). Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =1 ): Updated/Changed Cycle time, SPICLK from 40ns to 20ns; Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =1): Updated/Changed Pulse duration, SPICLK i.e. [Q2, Q3] from 0.5tc(SPC)M +- 4 to 0.5tc(SPC)M +- 2(Min/Max). Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =1): Updated/Changed Delay time, SPISIMO valid before SPICLK low, i.e. [Q4] from 0.5tc(SPC)M – 14 to 0.5tc(SPC)M – 7 (Min). Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =1): Updated/Changed Valid time, SPISIMO data valid after SPICLK low, i.e. [Q5] from 0.5tc(SPC)M – 18 to 0.5tc(SPC)M – 8 (Min). Go
  • (SPI Controller Mode Switching Parameters, Clock Phase =1): Updated/Changed Hold time, SPISOMI data valid after SPICLK i.e. [Q9] from 3ns to 2ns (Min). Go
  • (SPI Peripheral Mode Switching Parameters ): Updated/Changed Cycle time, SPICLK from 50ns to 20ns; Go
  • (SPI Peripheral Mode Switching Parameters ): Updated/Changed Pulse duration, SPICLK i.e. [Q2, Q3] from 20ns to 8ns (Min). Go
  • (SPI Peripheral Mode Switching Parameters ): Updated/Changed Setup time, SPISIMO before SPICLK i.e. [Q6] from 6ns to 2.1ns (Min). Go
  • (RGMII Receive Data and Control Timing Requirements): Updated/Changed Hold time, i.e. [No. 6] from 4.5ns to 1ns (Min). Go
  • (RMII Transmit Data and Control Switching Characteristics): Updated/Changed Delay time, REF_CLK high to selected transmit signals valid, i.e. [RMII 11] from 3ns to 2ns (Min). Go
  • (MII Transmit Switching Characteristics): Updated/Changed Delay time, miin_txclk to transmit selected signals valid, i.e. [No. 1] from 3ns to 0ns (Min). Go
  • (LVDS Interface Configuration) : Corrected a typo for the number of data lanes in LVDS from '4' to '2'Go
  • (Switching Characteristics for IEEE 1149.1 JTAG): Updated/Changed Delay time, TCK low to TDO valid, i.e. [No. 2] from 27.1ns to 21ns (Max). Go
  • (ADC Channels (Service) for User Application): Added a figure in the sectionGo
  • (Monitoring and Diagnostic Mechanisms): Updated the section and added a note for reference to safety related collateral. Go
  • (Monitoring and Diagnostic Mechanisms): Removed CRC-8 support since polynomials are not supported in the Design.Go