SLUSCE2D April 2016 – January 2019
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
INPUT | ||||||
tDGL(OVP_SET) | Input over-voltage blanking time | VIN: 5 V to 12 V | 113 | µs | ||
tDGL(OVP_REC) | Deglitch time exiting OVP | Time measured from VIN: 12V to 5V | 30 | µs | ||
ISET SHORT CIRCUIT TEST | ||||||
tDGL_SHORT | Deglitch time transition from ISET short to IOUT disable | Clear fault by disconnecting IN or cycling (high / low) TS | 1 | ms | ||
PRECHARGE – SET INTERNALLY | ||||||
tDGL1(LOWV) | Deglitch time on pre-charge to fast-charge transition | 70 | µs | |||
tDGL2(LOWV) | Deglitch time on fast-charge to pre-charge transition | 32 | ms | |||
TERMINATION | ||||||
tDGL(TERM) | Deglitch time, termination detected | 29 | ms | |||
RECHARGE OR REFRESH | ||||||
tDGL1(RCHG) | Deglitch time, recharge threshold detected | VIN = 5 V, VTS = 0.5 V, VOUT: 4.25 V to 3.5 V in 1 µs; tDGL(RCHG) is time to ISET ramp | 29 | ms | ||
BATTERY DETECT ROUTINE | ||||||
tDGL(HI/LOW REG) | Regulation time at VREG or VREG-BD | 25 | ms | |||
BATTERY-PACK NTC MONITOR; TS TERMINAL | ||||||
tDGL(TS) | Deglitch for TS thresholds: 0/45C. | Battery charging | 30 | ms |