SLUSAH0F October   2011  – November 2019 BQ25504


  1. Features
  2. Applications
  3. Description
    1.     Solar Application Circuit
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Maximum Power Point Tracking
      2. 8.3.2 Battery Undervoltage Protection
      3. 8.3.3 Battery Overvoltage Protection
      4. 8.3.4 Battery Voltage in Operating Range (VBAT_OK Output)
      5. 8.3.5 Nano-Power Management and Efficiency
    4. 8.4 Device Functional Modes
      1. 8.4.1 Cold-Start Operation (VSTOR < VSTOR_CHGEN, VIN_DC > VIN(CS) and PIN > PIN(CS))
      2. 8.4.2 Main Boost Charger Enabled (VSTOR > VSTOR_CHGEN, VIN_DC > VIN(DC) and EN = LOW )
      3. 8.4.3 Thermal Shutdown
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Storage Element Selection
      2. 9.1.2 Inductor Selection
      3. 9.1.3 Capacitor Selection
        1. VREF_SAMP Capacitance
        2. VIN_DC Capacitance
        3. VSTOR Capacitance
        4. Additional Capacitance on VSTOR or VBAT
    2. 9.2 Typical Applications
      1. 9.2.1 Solar Application Circuit
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 9.2.2 TEG Application Circuit
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 9.2.3 MPPT Disabled, Low Impedance Source Application Circuit
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Zip Files
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

As for all switching power supplies, the PCB layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the boost charger could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground paths. The input and output capacitors as well as the inductors should be placed as close as possible to the IC. For the boost charger, first priority are the output capacitors, including the 0.1 uF bypass capacitor (CBYP), followed by CSTOR, which should be placed as close as possible between VSTOR, pin 15, and VSS, pin 1 or 13. Next, the input capacitor, CIN, should be placed as close as possible between VIN_DC, pin 2, and VSS, pin 1. Last in priority is the boost charger inductor, L1, which should be placed close to LBOOST, pin 16, and VIN_DC, pin 2 if possible. It is best to use vias and bottom traces for connecting the inductor to its respective pins instead of the capacitors.

To minimize noise pickup by the high impedance voltage setting nodes (VBAT_OV, VBAT_UV, OK_PROG, OK_HYST), the external resistors should be placed so that the traces connecting the midpoints of each divider to their respective pins are as short as possible. When laying out the non-power ground return paths (e.g. from resistors and CREF), it is recommended to use short traces as well, separated from the power ground traces and connected to AVSS pin 12. This avoids ground shift problems, which can occur due to superimposition of power ground current and control ground current. The PowerPad should not be used as a power ground return path.

The remaining pins are digital signals with minimal layout restrictions. See Figure 34 for an example layout.

In order to maximize efficiency at light load, the use of voltage level setting resistors > 1 MΩ is recommended. In addition, the sample and hold circuit output capacitor on VREF_SAMP must hold the voltage for 16 s. During board assembly, contaminants such as solder flux and even some board cleaning agents can leave residue that may form parasitic resistors across the physical resistors/capacitors and/or from one end of a resistor/capacitor to ground, especially in humid, fast airflow environments. This can result in the voltage regulation and threshold levels changing significantly from those expected per the installed components. Therefore, it is highly recommended that no ground planes be poured near the voltage setting resistors or the sample and hold capacitor. In addition, the boards must be carefully cleaned, possibly rotated at least once during cleaning, and then rinsed with de-ionized water until the ionic contamination of that water is well above 50 Mohm. If this is not feasible, then it is recommended that the sum of the voltage setting resistors be reduced to at least 5X below the measured ionic contamination.