SLUSC53B May 2015 – May 2018
PRODUCTION DATA.
Some bq27546-G1 pins are configured via the Pack Configuration B data flash register, as indicated in Table 10. This register is programmed/read via the methods described in the bq27546-G1 Technical Reference Manual (SLUUB74). The register is located at Subclass = 64, offset = 2.
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | |
---|---|---|---|---|---|---|---|---|
ChgDoD
EoC |
SE_TDD | VconsEN | SE_ISD | RSVD | LFPRelax | DoDWT | FConvEn | |
Default = | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 |
0x67 |
ChgDoDEoC = | Enable DoD at EoC recalculation during charging only. True when set. The default setting is recommended. |
SE_TDD = | Enable Tab Disconnection Detection. True when set. |
VconsEN = | Enable voltage consistency check. True when set. The default setting is recommended. |
SE_ISD = | Enable Internal Short Detection. True when set. |
RSVD = | Reserved. Must be 0. |
LFPRelax = | Enable LiFePO4 long relaxation mode. True when set. |
DoDWT = | Enable DoD weighting feature of gauging algorithm. This feature can improve accuracy during relaxation in a flat portion of the voltage profile, especially when using LiFePO4 chemistry. True when set. |
FConvEn = | Enable fast convergence algorithm. The default setting is recommended. |