SLUS900E December   2008  – August 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IRQ Function
      2. 7.3.2 VBACK Switchover
      3. 7.3.3 Trickle Charge
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 I2C Read After Backup Mode
      2. 7.6.2 Normal Register Descriptions
        1. 7.6.2.1  SECONDS Register (address = 0x00) [reset = 0XXXXXXb]
        2. 7.6.2.2  MINUTES Register (address = 0x01) [reset = 1XXXXXXb]
        3. 7.6.2.3  CENT_HOURS Register (address = 0x02) [reset = XXXXXXXXb]
        4. 7.6.2.4  DAY Register (address = 0x03) [reset = 00000XXXb]
        5. 7.6.2.5  DATE Register (address = 0x04) [reset = 00XXXXXXb]
        6. 7.6.2.6  MONTH Register (address = 0x05) [reset = 000XXXXXb]
        7. 7.6.2.7  YEARS Register (address = 0x06) [reset = XXXXXXXXb]
        8. 7.6.2.8  CAL_CFG1 Register (address = 0x07) [reset = 10000000b]
        9. 7.6.2.9  TCH2 Register (address = 0x08) [reset = 10010000b]
        10. 7.6.2.10 CFG2 Register (address = 0x09) [reset = 10101010b]
      3. 7.6.3 Special Function Registers
        1. 7.6.3.1 SF KEY 1 Register (address = 0x20) [reset = 00000000b]
        2. 7.6.3.2 SF KEY 2 Register (address = 0x21) [reset = 00000000b]
        3. 7.6.3.3 SFR Register (address = 0x22) [reset = 00000000b]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reading From a Register
        2. 8.2.2.2 Leap Year Compensation
        3. 8.2.2.3 Utilizing the Backup Supply
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The VCC pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a minimum recommended value of 1-µF. This capacitor should be placed as close to the VCC and GND pins as possible with thick trace or ground plane connection to the device GND pin.

Locate the 32.768-kHz crystal oscillator as close as possible to the OSCI and OSCO pins. This will minimize stray capacitance.

10.2 Layout Example

bq32000 layout_slus900.gifFigure 25. Recommended PCB Layout