SLUSCG1 September   2018

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Digital Input and Output DC Characteristics
    7. 6.7  LDO Regulator, Wake-up, and Auto-Shutdown DC Characteristics
    8. 6.8  LDO Regulator, Wake-up, and Auto-Shutdown AC Characteristics
    9. 6.9  ADC (Temperature and Cell Measurement) Characteristics
    10. 6.10 Integrating ADC (Coulomb Counter) Characteristics
    11. 6.11 I2C-Compatible Interface Communication Timing
    12. 6.12 SHUTDOWN and WAKE-UP Timing
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Configuration
      2. 7.3.2  ALERT Interrupt and SHUTDOWN Wake-up
      3. 7.3.3  Voltage Measurement and Calibration
      4. 7.3.4  Temperature Measurement
      5. 7.3.5  Charging and Termination
      6. 7.3.6  Accumulated Charge Measurement
      7. 7.3.7  Gas Gauging
      8. 7.3.8  Battery Condition Warnings
      9. 7.3.9  Configuration Update
      10. 7.3.10 End-Of-Service Determination
      11. 7.3.11 Battery Level Threshold
      12. 7.3.12 Communications
        1. 7.3.12.1 I2C Interface
        2. 7.3.12.2 I2C Time Out
        3. 7.3.12.3 I2C Command Waiting Time
        4. 7.3.12.4 I2C Clock Stretching
      13. 7.3.13 Additional Data Memory Parameter Descriptions
    4. 7.4 Device Functional Modes
      1. 7.4.1 INITIALIZATION Mode
      2. 7.4.2 NORMAL Mode
      3. 7.4.3 SLEEP Mode
      4. 7.4.4 SHUTDOWN Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Getting Started
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 REGIN Voltage Sense Input
        2. 8.2.2.2 Integrated LDO Capacitor
        3. 8.2.2.3 Sense Resistor Selection
      3. 8.2.3 External Thermistor Support
      4. 8.2.4 Learning Load Enable (LEN) from Host
      5. 8.2.5 I2C
      6. 8.2.6 Temperature Sense
      7. 8.2.7 Application Curves
  9. 9 Power Supply Recommendation
    1. 9.1 Power Supply Decoupling
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.11 I2C-Compatible Interface Communication Timing

TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1)(1)
MIN NOM MAX UNIT
Standard Mode (100 kHz)
td(STA) Start to first falling edge of SCL 4 µs
tw(L) SCL pulse duration (low) 4.7 µs
tw(H) SCL pulse duration (high) 4 µs
tsu(STA) Setup for repeated start 4.7 µs
tsu(DAT) Data setup time Host drives SDA 250 ns
th(DAT) Data hold time Host drives SDA 0 ns
tsu(STOP) Setup time for stop 4 µs
t(BUF) Bus free time between stop and start Includes Command Waiting Time 66 µs
tf SCL or SDA fall time(1)(2) 300 ns
tr SCL or SDA rise time(1)(2) 300 ns
fSCL Clock frequency(3) 100 kHz
Fast Mode (400 kHz)
td(STA) Start to first falling edge of SCL 600 ns
tw(L) SCL pulse duration (low) 1300 ns
tw(H) SCL pulse duration (high) 600 ns
tsu(STA) Setup for repeated start 600 ns
tsu(DAT) Data setup time Host drives SDA 100 ns
th(DAT) Data hold time Host drives SDA 0 ns
tsu(STOP) Setup time for stop 600 ns
t(BUF) Bus free time between stop and start Includes Command Waiting Time 66 µs
tf SCL or SDA fall time(1)(2) 300 ns
tr SCL or SDA rise time(1)(2) 300 ns
fSCL Clock frequency(3) 400 kHz
(1) Specified by design. Not production tested.
(2) Bus capacitance and pull-up resistance impact rise and fall times. View the rise and fall times to assist with debugging.
(3) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (See I2C Interface and I2C Command Waiting Time.)
bq34210-Q1 tim_dia_i2c.gifFigure 1. I2C-Compatible Interface Timing Diagrams