SLUSCB3 July   2015


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: Supply Current
    6. 7.6  Electrical Characteristics: Power Supply Control
    7. 7.7  Electrical Characteristics: AFE Power-On Reset
    8. 7.8  Electrical Characteristics: AFE Watchdog Reset and Wake Timer
    9. 7.9  Electrical Characteristics: Current Wake Comparator
    10. 7.10 Electrical Characteristics: VC1, VC2, VC3, VC4, BAT, PACK
    11. 7.11 Electrical Characteristics: SMBD, SMBC
    12. 7.12 Electrical Characteristics: PRES, BTP_INT, DISP
    13. 7.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB, LEDCNTLC
    14. 7.14 Electrical Characteristics: Coulomb Counter
    15. 7.15 Electrical Characteristics: CC Digital Filter
    16. 7.16 Electrical Characteristics: ADC
    17. 7.17 Electrical Characteristics: ADC Digital Filter
    18. 7.18 Electrical Characteristics: CHG, DSG FET Drive
    19. 7.19 Electrical Characteristics: PCHG FET Drive
    20. 7.20 Electrical Characteristics: FUSE Drive
    21. 7.21 Electrical Characteristics: Internal Temperature Sensor
    22. 7.22 Electrical Characteristics: TS1, TS2, TS3, TS4
    23. 7.23 Electrical Characteristics: PTC, PTCEN
    24. 7.24 Electrical Characteristics: Internal 1.8-V LDO
    25. 7.25 Electrical Characteristics: High-Frequency Oscillator
    26. 7.26 Electrical Characteristics: Low-Frequency Oscillator
    27. 7.27 Electrical Characteristics: Voltage Reference 1
    28. 7.28 Electrical Characteristics: Voltage Reference 2
    29. 7.29 Electrical Characteristics: Instruction Flash
    30. 7.30 Electrical Characteristics: Data Flash
    31. 7.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2 Current Protection Thresholds
    32. 7.32 Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing
    33. 7.33 Timing Requirements: SMBus
    34. 7.34 Timing Requirements: SMBus XL
    35. 7.35 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Primary (1st Level) Safety Features
      2. 8.3.2  Secondary (2nd Level) Safety Features
      3. 8.3.3  Charge Control Features
      4. 8.3.4  Gas Gauging
      5. 8.3.5  Configuration
        1. Oscillator Function
        2. System Present Operation
        3. Emergency Shutdown
        4. 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration
        5. Cell Balancing
      6. 8.3.6  Battery Parameter Measurements
        1. Charge and Discharge Counting
      7. 8.3.7  Battery Trip Point (BTP)
      8. 8.3.8  Lifetime Data Logging Features
      9. 8.3.9  Authentication
      10. 8.3.10 LED Display
      11. 8.3.11 Voltage
      12. 8.3.12 Current
      13. 8.3.13 Temperature
      14. 8.3.14 Communications
        1. SMBus On and Off State
        2. SBS Commands
    4. 8.4 Device Functional Modes
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. High-Current Path
          1. Protection FETs
          2. Chemical Fuse
          3. Lithium-Ion Cell Connections
          4. Sense Resistor
          5. ESD Mitigation
        2. Gas Gauge Circuit
          1. Coulomb-Counting Interface
          2. Power Supply Decoupling and PBI
          3. System Present
          4. SMBus Communication
          5. FUSE Circuitry
        3. Secondary-Current Protection
          1. Cell and Battery Inputs
          2. External Cell Balancing
          3. PACK and FET Control
          4. Temperature Output
          5. LEDs
          6. Safety PTC Thermistor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 11.1.2 ESD Spark Gap
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Applications and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The bq40z50-R1 is a gas gauge with primary protection support, and that can be used with a 1-series to 4-series Li-Ion/Li Polymer battery pack. To implement and design a comprehensive set of parameters for a specific battery pack, users need the Battery Management Studio (bqSTUDIO) graphical user-interface tool installed on a PC during development. The firmware installed on the bqSTUDIO tool has default values for this product, which are summarized in the bq40z50-R1 Technical Reference Manual (SLUUBC1). Using the bqSTUDIO tool, these default values can be changed to cater to specific application requirements during development once the system parameters, such as fault trigger thresholds for protection, enable/disable of certain features for operation, configuration of cells, chemistry that best matches the cell used, and more are known. This data is referred to as the "golden image."

9.2 Typical Applications

bq40z50-R1 Schematic_BandW.gifFigure 21. Application Schematic

9.2.1 Design Requirements

Table 1 shows the default settings for the main parameters. Use the bqSTUDIO tool to update the settings to meet the specific application or battery pack configuration requirements.

The device should be calibrated before any gauging test. Follow the bqSTUDIO Calibration page to calibrate the device, and use the bqSTUDIO Chemistry page to update the match chemistry profile to the device.

Table 1. Design Parameters

Cell Configuration 3s1p (3-series with 1 Parallel)(1)
Design Capacity 4400 mAh
Device Chemistry 1210 (LiCoO2/graphitized carbon)
Cell Overvoltage at Standard Temperature 4300 mV
Cell Undervoltage 2500 mV
Shutdown Voltage 2300 mV
Overcurrent in CHARGE Mode 6000 mA
Overcurrent in DISCHARGE Mode –6000 mA
Short Circuit in CHARGE Mode 0.1 V/Rsense across SRP, SRN
Short Circuit in DISCHARGE Mode 0.1 V/Rsense across SRP, SRN
Safety Overvoltage 4500 mV
Cell Balancing Disabled
Internal and External Temperature Sensor External Temperature Sensor is used.
Undertemperature Charging 0°C
Undertemperature Discharging 0°C
BROADCAST Mode Disabled
Battery Trip Point (BTP) with active high interrupt Disabled
(1) When using the device the first time, if the a 1-s or 2-s battery pack is used, then a charger or power supply should be connected to the PACK+ terminal to prevent device shutdown. Then update the cell configuration (see the bq40z50-R1 Technical Reference Manual [SLUUBC1] for details) before removing the charger connection.

9.2.2 Detailed Design Procedure High-Current Path

The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell connections, and the sense resistor, and then returns to the PACK– terminal (see Figure 22). In addition, some components are placed across the PACK+ and PACK– terminals to reduce effects from electrostatic discharge. Protection FETs

Select the N-channel charge and discharge FETs for a given application. Most portable battery applications are a good match for the CSD17308Q3. The TI CSD17308Q3 is a 47A, 30-V device with Rds(on) of 8.2 mΩ when the gate drive voltage is 8 V.

If a precharge FET is used, R1 is calculated to limit the precharge current to the desired rate. Be sure to account for the power dissipation of the series resistor. The precharge current is limited to (VCHARGER – VBAT)/R1 and maximum power dissipation is (Vcharger – Vbat)2/R1.

The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source to ensure they are turned off if the gate drive is open.

Capacitors C1 and C2 help protect the FETs during an ESD event. Using two devices ensures normal operation if one becomes shorted. To have good ESD protection, the copper trace inductance of the capacitor leads must be designed to be as short and wide as possible. Ensure that the voltage rating of both C1 and C2 are adequate to hold off the applied voltage if one of the capacitors becomes shorted.

bq40z50-R1 device_protect_FET_lua660.gifFigure 22. bq40z50-R1 Protection FETs Chemical Fuse

The chemical fuse (Dexerials, Uchihashi, and so forth) is ignited under command from either the bq294700 secondary voltage protection IC or from the FUSE pin of the gas gauge. Either of these events applies a positive voltage to the gate of Q5, shown in Figure 23, which then sinks current from the third terminal of the fuse, causing it to ignite and open permanently.

It is important to carefully review the fuse specifications and match the required ignition current to that available from the N-channel FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device. The fuse control circuit is discussed in detail in FUSE Circuitry.

bq40z50-R1 FUSE_circuit_lau660.gifFigure 23. FUSE Circuit Lithium-Ion Cell Connections

The important part to remember about the cell connections is that high current flows through the top and bottom connections; therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid any errors due to a drop in the high-current copper trace. The location marked 4P in Figure 24 indicates the Kelvin connection of the most positive battery node. The connection marked 1N is equally important. The VC5 pin (a ground reference for cell voltage measurement), which is in the older generation devices, is not in the bq40z50-R1 device. Therefore, the single-point connection at 1N to the low-current ground is needed to avoid an undesired voltage drop through long traces while the gas gauge is measuring the bottom cell voltage.

bq40z50-R1 li_ion_cell_conn_lua660.gifFigure 24. Lithium-Ion Cell Connections Sense Resistor

As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and short-circuit ranges of the bq40z50-R1. Select the smallest value possible to minimize the negative voltage generated on the bq40z50-R1 VSS node(s) during a short circuit. This pin has an absolute minimum of –0.3 V. Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to support a 1-mΩ to 3-mΩ sense resistor.

The ground scheme of bq40z50-R1 is different from the older generation devices. In previous devices, the device ground (or low current ground) is connected to the SRN side of the Rsense resistor pad. The bq40z50-R1, however, connects the low-current ground on the SRP side of the Rsense resistor pad, close to the battery 1N terminal (see Lithium-Ion Cell Connections). This is because the bq40z50-R1 has one less VC pin (a ground reference pin VC5) compared to the previous devices. The pin was removed and was internally combined to SRP.

bq40z50-R1 sense_resis_lua660.gifFigure 25. Sense Resistor ESD Mitigation

A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– terminals to help in the mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack if one of the capacitors becomes shorted.

Optionally, a tranzorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity. Gas Gauge Circuit

The Gas Gauge Circuit includes the bq40z50-R1 and its peripheral components. These components are divided into the following groups: Differential Low-Pass Filter, PBI, System Present, SMBus Communication, FUSE circuit, and LED. Coulomb-Counting Interface

The bq40z50-R1 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from the sense resistor to the SRP and SRN inputs of the device. Place a 0.1-µF (C18) filter capacitor across the SRP and SRN inputs. Optional 0.1-µF filter capacitors (C19 and C20) can be added for additional noise filtering, if required for your circuit.

bq40z50-R1 diff_filter.gifFigure 26. Differential Filter Power Supply Decoupling and PBI

The bq40z50-R1 has an internal LDO that is internally compensated and does not require an external decoupling capacitor.

The PBI pin is used as a power supply backup input pin providing power during brief transient power outages. A standard 2.2-µF ceramic capacitor is connected from the PBI pin to ground as shown in Figure 27.

bq40z50-R1 p_s_decoupling_lua660.gifFigure 27. Power Supply Decoupling System Present

The System Present signal is used to inform the gas gauge whether the pack is installed into or removed from the system. In the host system, this pin is grounded. The PRES pin of the bq40z50-R1 is occasionally sampled to test for system present. To save power, an internal pullup is provided by the gas gauge during a brief 4-μs sampling pulse once per second. A resistor can be used to pull the signal low and the resistance must be 20 kΩ or lower to insure that the test pulse is lower than the VIL limit. The pull-up current source is typically 10 µA to 20 µA.

bq40z50-R1 nfig07a_SLUA660.pngFigure 28. System Present Pull-Down Resistor

Because the System Present signal is part of the pack connector interface to the outside world, it must be protected from external electrostatic discharge events. An integrated ESD protection on the PRES device pin reduces the external protection requirement to just R29 for an 8-kV ESD contact rating. However, if it is possible that the System Present signal may short to PACK+, then R28 and D4 must be included for high-voltage protection.

bq40z50-R1 sys_present_ESD_lua660.gifFigure 29. System Present ESD and Short Protection SMBus Communication

The SMBus clock and data pins have integrated high-voltage ESD protection circuits, however, adding a Zener diode (D2 and D3) and series resistor (R24 and R26) provides more robust ESD performance.

The SMBus clock and data lines have internal pulldown. When the gas gauge senses that both lines are low (such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP mode to conserve power.

bq40z50-R1 ESD_protect_SMB_comm_lua660.gifFigure 30. ESD Protection for SMB Communication FUSE Circuitry

The FUSE pin of the bq40z50-R1 is designed to ignite the chemical fuse if one of the various safety criteria is violated. The FUSE pin also monitors the state of the secondary-voltage protection IC. Q5 ignites the chemical fuse when its gate is high. The 7-V output of the bq294700 is divided by R16 and R6, which provides adequate gate drive for Q5 while guarding against excessive back current into the bq294700 if the FUSE signal is high.

Using C3 is generally a good practice, especially for RFI immunity. C3 may be removed, if desired, because the chemical fuse is a comparatively slow device and is not affected by any sub-microsecond glitches that come from the FUSE output during the cell connection process.

bq40z50-R1 FUSE_circuit_lau660.gifFigure 31. FUSE Circuit

When the bq40z50-R1 is commanded to ignite the chemical fuse, the FUSE pin activates to give a typical 8-V output. The new design makes it possible to use a higher Vgs FET for Q5. This improves the robustness of the system, as well as widens the choices for Q5. Secondary-Current Protection

The bq40z50-R1 provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage multiplexing, and voltage translation. The following discussion examines Cell and Battery Inputs, Pack and FET Control, Temperature Output, and Cell Balancing. Cell and Battery Inputs

Each cell input is conditioned with a simple RC filter, which provides ESD protection during cell connect and acts to filter unwanted voltage transients. The resistor value allows some trade-off for cell balancing versus safety protection.

The integrated cell balancing FETs allow the AFE to bypass cell current around a given cell or numerous cells, effectively balancing the entire battery stack. External series resistors placed between the cell connections and the VCx I/O pins set the balancing current magnitude. The internal FETs provide a 200-Ω resistance (2 V < VDS < 4 V). Series input resistors between 100 Ω and 1 kΩ are recommended for effective cell balancing.

The BAT input uses a diode (D1) to isolate and decouple it from the cells in the event of a transient dip in voltage caused by a short-circuit event.

Also, as described in High-Current Path, the top and bottom nodes of the cells must be sensed at the battery connections with a Kelvin connection to prevent voltage sensing errors caused by a drop in the high-current PCB copper.

bq40z50-R1 cell_and_BAT_in_lua660.gifFigure 32. Cell and BAT Inputs External Cell Balancing

Internal cell balancing can only support up to 10 mA. External cell balancing provide as another option for faster cell balancing. For details, refer to the application note, Fast Cell Balancing Using External MOSFET (SLUA420). PACK and FET Control

The PACK and VCC inputs provide power to the bq40z50-R1 from the charger. The PACK input also provides a method to measure and detect the presence of a charger. The PACK input uses a 100-Ω resistor; whereas, the VCC input uses a diode to guard against input transients and prevents mis-operation of the date driver during short-circuit events.

bq40z50-R1 device_PACK_FET_cont_lua660.gifFigure 33. bq40z50-R1 PACK and FET Control

The N-channel charge and discharge FETs are controlled with 5.1-kΩ series gate resistors, which provide a switching time constant of a few microseconds. The 10-MΩ resistors ensure that the FETs are off in the event of an open connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a reverse-connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the PACK+ input becomes slightly negative.

Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the FET must have a low gate turn-on threshold. If it is desired to use a more standard device, such as the 2N7002 as the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor. The bq40z50-R1 device has the capability to provide a current-limited charging path typically used for low battery voltage or low temperature charging. The bq40z50-R1 device uses an external P-channel, pre-charge FET controlled by PCHG. Temperature Output

For the bq40z50-R1 device, TS1, TS2, TS3, and TS4 provide thermistor drive-under program control. Each pin can be enabled with an integrated 18-kΩ (typical) linearization pullup resistor to support the use of a 10-kΩ at 25°C (103) NTC external thermistor such as a Mitsubishi BN35-3H103. The reference design includes four 10-kΩ thermistors: RT1, RT2, RT3, and RT4. The bq40z50-R1 device supports up to four external thermistors. Connect unused thermistor pins to VSS.

bq40z50-R1 thermistor_drive_lua660.gifFigure 34. Thermistor Drive LEDs

Three LED control outputs provide constant current sinks for the driving external LEDs. These outputs are configured to provide voltage and control for up to 5 LEDs. No external bias voltage is required. Unused LEDCNTL pins can remain open or they can be connected to VSS. The DISP pin should be connected to VSS, if the LED feature is not used.

bq40z50-R1 LEDs_lua660.gifFigure 35. LEDs Safety PTC Thermistor

The bq40z50-R1 device provides support for a safety PTC thermistor. The PTC thermistor is connected between the PTC pin and VSS. It can be placed close to the CHG/DSG FETs to monitor the temperature. The PTC pin outputs a very small current, typical ~370 nA, and the PTC fault will be triggered at ~0.7 V typical. A PTC fault is one of the permanent failure modes. It can only be cleared by a POR.

To disable this feature, connect a 10-kΩ resistor between PTC and VSS.

bq40z50-R1 PTC_thermistor_lua660.gifFigure 36. PTC Thermistor

9.2.3 Application Curves

bq40z50-R1 C009_SLUSAS3.png
Threshold setting is 25 mV.
Figure 37. Overcurrent Discharge Protection Threshold Vs. Temperature
bq40z50-R1 C011_SLUSAS3.png
Threshold setting is –88.85 mV.
Figure 39. Short Circuit Discharge 1 Protection Threshold Vs. Temperature
bq40z50-R1 C013_SLUSAS3.png
Threshold setting is 11 ms.
Figure 41. Overcurrent Delay Time Vs. Temperature
bq40z50-R1 C010_SLUSAS3.png
Threshold setting is 25 mV.
Figure 38. Short Circuit Charge Protection Threshold Vs. Temperature
bq40z50-R1 C012_SLUSAS3.png
Threshold setting is –177.7 mV.
Figure 40. Short Circuit Discharge 2 Protection Threshold Vs. Temperature
bq40z50-R1 C014_SLUSAS3.png
Threshold setting is 465 µs.
Figure 42. Short Circuit Charge Current Delay Time Vs. Temperature