SLUSCS4C June   2017  – April 2021 BQ40Z50-R2

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Equivalent Diagrams
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Power Supply Control
    7. 7.7  AFE Power-On Reset
    8. 7.8  AFE Watchdog Reset and Wake Timer
    9. 7.9  Current Wake Comparator
    10. 7.10 VC1, VC2, VC3, VC4, BAT, PACK
    11. 7.11 SMBD, SMBC
    12. 7.12 PRES, BTP_INT, DISP
    13. 7.13 LEDCNTLA, LEDCNTLB, LEDCNTLC
    14. 7.14 Coulomb Counter
    15. 7.15 CC Digital Filter
    16. 7.16 ADC
    17. 7.17 ADC Digital Filter
    18. 7.18 CHG, DSG FET Drive
    19. 7.19 PCHG FET Drive
    20. 7.20 FUSE Drive
    21. 7.21 Internal Temperature Sensor
    22. 7.22 TS1, TS2, TS3, TS4
    23. 7.23 PTC, PTCEN
    24. 7.24 Internal 1.8-V LDO
    25. 7.25 High-Frequency Oscillator
    26. 7.26 Low-Frequency Oscillator
    27. 7.27 Voltage Reference 1
    28. 7.28 Voltage Reference 2
    29. 7.29 Instruction Flash
    30. 7.30 Data Flash
    31. 7.31 OLD, SCC, SCD1, SCD2 Current Protection Thresholds
    32. 7.32 Timing Requirements: OLD, SCC, SCD1, SCD2 Current Protection Timing
    33. 7.33 Timing Requirements: SMBus
    34. 7.34 Timing Requirements: SMBus XL
    35. 7.35 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Primary (1st Level) Safety Features
      2. 8.3.2  Secondary (2nd Level) Safety Features
      3. 8.3.3  Charge Control Features
      4. 8.3.4  Gas Gauging
      5. 8.3.5  Configuration
        1. 8.3.5.1 Oscillator Function
        2. 8.3.5.2 System Present Operation
        3. 8.3.5.3 Emergency Shutdown
        4. 8.3.5.4 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration
        5. 8.3.5.5 Cell Balancing
      6. 8.3.6  Battery Parameter Measurements
        1. 8.3.6.1 Charge and Discharge Counting
      7. 8.3.7  Battery Trip Point (BTP)
      8. 8.3.8  Lifetime Data Logging Features
      9. 8.3.9  Authentication
      10. 8.3.10 LED Display
      11. 8.3.11 IATA Support
      12. 8.3.12 Voltage
      13. 8.3.13 Current
      14. 8.3.14 Temperature
      15. 8.3.15 Communications
        1. 8.3.15.1 SMBus On and Off State
        2. 8.3.15.2 SBS Commands
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 High-Current Path
          1. 9.2.2.1.1 Protection FETs
          2. 9.2.2.1.2 Chemical Fuse
          3. 9.2.2.1.3 Li-Ion Cell Connections
          4. 9.2.2.1.4 Sense Resistor
          5. 9.2.2.1.5 ESD Mitigation
        2. 9.2.2.2 Gas Gauge Circuit
          1. 9.2.2.2.1 Coulomb-Counting Interface
          2. 9.2.2.2.2 Power Supply Decoupling and PBI
          3. 9.2.2.2.3 System Present
          4. 9.2.2.2.4 SMBus Communication
          5. 9.2.2.2.5 FUSE Circuitry
        3. 9.2.2.3 Secondary-Current Protection
          1. 9.2.2.3.1 Cell and Battery Inputs
          2. 9.2.2.3.2 External Cell Balancing
          3. 9.2.2.3.3 PACK and FET Control
          4. 9.2.2.3.4 Temperature Output
          5. 9.2.2.3.5 LEDs
          6. 9.2.2.3.6 Safety PTC Thermistor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 11.1.2 ESD Spark Gap
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
      2. 12.2.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.16 ADC

Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range Internal reference (VREF1) –0.2 1 V
External reference (VREG) –0.2 0.8 × VREG
Full scale range VFS = VREF1 or VREG –VFS VFS V
Integral nonlinearity(1) 16-bit, best fit, –0.1 V to 0.8 × VREF1 ±6.6 LSB
16-bit, best fit, –0.2 V to –0.1 V ±13.1
Offset error(2) 16-bit, Post-calibration, VFS = VREF1 ±67 ±157 µV
Offset error drift 16-bit, Post-calibration, VFS = VREF1 0.6 3 µV/°C
Gain error 16-bit, –0.1 V to 0.8 × VFS ±0.2% ±0.8% FSR
Gain error drift 16-bit, –0.1 V to 0.8 × VFS 150 PPM/°C
Effective input resistance 8 MΩ
(1) 1 LSB = VREF1/(2N) = 1.225/(215) = 37.4 µV (when tCONV = 31.25 ms)
(2) For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and VREF1/2, the offset error is multiplied by (1/ADC multiplexer scaling factor (K)).