SLUSCS4C June   2017  – April 2021 BQ40Z50-R2

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Equivalent Diagrams
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current
    6. 7.6  Power Supply Control
    7. 7.7  AFE Power-On Reset
    8. 7.8  AFE Watchdog Reset and Wake Timer
    9. 7.9  Current Wake Comparator
    10. 7.10 VC1, VC2, VC3, VC4, BAT, PACK
    11. 7.11 SMBD, SMBC
    12. 7.12 PRES, BTP_INT, DISP
    13. 7.13 LEDCNTLA, LEDCNTLB, LEDCNTLC
    14. 7.14 Coulomb Counter
    15. 7.15 CC Digital Filter
    16. 7.16 ADC
    17. 7.17 ADC Digital Filter
    18. 7.18 CHG, DSG FET Drive
    19. 7.19 PCHG FET Drive
    20. 7.20 FUSE Drive
    21. 7.21 Internal Temperature Sensor
    22. 7.22 TS1, TS2, TS3, TS4
    23. 7.23 PTC, PTCEN
    24. 7.24 Internal 1.8-V LDO
    25. 7.25 High-Frequency Oscillator
    26. 7.26 Low-Frequency Oscillator
    27. 7.27 Voltage Reference 1
    28. 7.28 Voltage Reference 2
    29. 7.29 Instruction Flash
    30. 7.30 Data Flash
    31. 7.31 OLD, SCC, SCD1, SCD2 Current Protection Thresholds
    32. 7.32 Timing Requirements: OLD, SCC, SCD1, SCD2 Current Protection Timing
    33. 7.33 Timing Requirements: SMBus
    34. 7.34 Timing Requirements: SMBus XL
    35. 7.35 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Primary (1st Level) Safety Features
      2. 8.3.2  Secondary (2nd Level) Safety Features
      3. 8.3.3  Charge Control Features
      4. 8.3.4  Gas Gauging
      5. 8.3.5  Configuration
        1. 8.3.5.1 Oscillator Function
        2. 8.3.5.2 System Present Operation
        3. 8.3.5.3 Emergency Shutdown
        4. 8.3.5.4 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration
        5. 8.3.5.5 Cell Balancing
      6. 8.3.6  Battery Parameter Measurements
        1. 8.3.6.1 Charge and Discharge Counting
      7. 8.3.7  Battery Trip Point (BTP)
      8. 8.3.8  Lifetime Data Logging Features
      9. 8.3.9  Authentication
      10. 8.3.10 LED Display
      11. 8.3.11 IATA Support
      12. 8.3.12 Voltage
      13. 8.3.13 Current
      14. 8.3.14 Temperature
      15. 8.3.15 Communications
        1. 8.3.15.1 SMBus On and Off State
        2. 8.3.15.2 SBS Commands
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 High-Current Path
          1. 9.2.2.1.1 Protection FETs
          2. 9.2.2.1.2 Chemical Fuse
          3. 9.2.2.1.3 Li-Ion Cell Connections
          4. 9.2.2.1.4 Sense Resistor
          5. 9.2.2.1.5 ESD Mitigation
        2. 9.2.2.2 Gas Gauge Circuit
          1. 9.2.2.2.1 Coulomb-Counting Interface
          2. 9.2.2.2.2 Power Supply Decoupling and PBI
          3. 9.2.2.2.3 System Present
          4. 9.2.2.2.4 SMBus Communication
          5. 9.2.2.2.5 FUSE Circuitry
        3. 9.2.2.3 Secondary-Current Protection
          1. 9.2.2.3.1 Cell and Battery Inputs
          2. 9.2.2.3.2 External Cell Balancing
          3. 9.2.2.3.3 PACK and FET Control
          4. 9.2.2.3.4 Temperature Output
          5. 9.2.2.3.5 LEDs
          6. 9.2.2.3.6 Safety PTC Thermistor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 11.1.2 ESD Spark Gap
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
      2. 12.2.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

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Table 6-1 Pin Functions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1 PBI P(1) Power supply backup input pin. Connect to the 2.2-µF capacitor to VSS.
2 VC4 IA Sense voltage input pin for the most positive cell, and balance current input for the most positive cell. Should be connected to the positive terminal of the fourth cell from the bottom of the stack with a 100-Ω series resistor and a 0.1-μF capacitor to VC3. If not used, connect to VC3.
3 VC3 IA Sense voltage input pin for the third-most positive cell, balance current input for the third-most positive cell, and return balance current for the most positive cell. Should be connected to the positive terminal of the third cell from the bottom of the stack with a 100-Ω series resistor and a 0.1-μF capacitor to VC2. If not used, connect to VC2.
4 VC2 IA Sense voltage input pin for the second-most positive cell, balance current input for the second-most positive cell, and return balance current for the third-most positive cell. Should be connected to the positive terminal of the second cell from the bottom of the stack with a 100-Ω series resistor and a 0.1-μF capacitor to VC1. If not used, connect to VC1.
5 VC1 IA Sense voltage input pin for the least positive cell, balance current input for the least positive cell, and return balance current for the second-most positive cell. Should be connected to the positive terminal of the first cell from the bottom of the stack with a 100-Ω series resistor and a 0.1-μF capacitor to VSS.
6 SRN I Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor.
7 NC — Not internally connected. It is okay to leave floating or to tie to VSS.
8 SRP I Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor.
9 VSS P Device ground
10 TS1 IA Temperature sensor 1 thermistor input pin. Connect to thermistor-1. If not used, connect directly to VSS and configure data flash accordingly.
11 TS2 IA Temperature sensor 2 thermistor input pin. Connect to thermistor-2. If not used, connect directly to VSS and configure data flash accordingly.
12 TS3 IA Temperature sensor 3 thermistor input pin. Connect to thermistor-3. If not used, connect directly to VSS and configure data flash accordingly.
13 TS4 IA Temperature sensor 4 thermistor input pin. Connect to thermistor-4. If not used, connect directly to VSS and configure data flash accordingly.
14 NC — Not internally connected. It is okay to leave floating or to tie to VSS.
15 BTP_INT O Battery Trip Point (BTP) interrupt output. If not used, connect directly to VSS.
16 PRES or SHUTDN I Host system present input for removable battery pack or emergency system shutdown input for embedded pack. A pullup is not required for this pin. If not used, connect directly to VSS.
17 DISP — Display control for LEDs. If not used, connect directly to VSS.
18 SMBD I/OD SMBus data pin
19 SMBC I/OD SMBus clock pin
20 LEDCNTLA — LED display segment that drives the external LEDs depending on the firmware configuration. If LEDs are not used, these pins can be left floating or connected to VSS through a 20-kΩ resistor.
21 LEDCNTLB — LED display segment that drives the external LEDs depending on the firmware configuration. If LEDs are not used, these pins can be left floating or connected to VSS through a 20-kΩ resistor.
22 LEDCNTLC — LED display segment that drives the external LEDs depending on the firmware configuration. If LEDs are not used, these pins can be left floating or connected to VSS through a 20-kΩ resistor.
23 PTC IA Safety PTC thermistor input pin. To disable, connect both PTC and PTCEN to VSS.
24 PTCEN IA Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect both PTC and PTCEN to VSS.
25 FUSE O Fuse drive output pin. If not used, connect directly to VSS.
26 VCC P Secondary power supply input
27 PACK IA Pack sense input pin
28 DSG O NMOS Discharge FET drive output pin. If not used, it can be left floating or connected to VSS through a 20-kΩ resistor.
29 NC — Not internally connected. It is okay to leave floating or to tie to VSS.
30 PCHG O PMOS Precharge FET drive output pin. If not used, it can be left floating or connected to VSS through a 20-kΩ resistor.
31 CHG O NMOS Charge FET drive output pin. If not used, it can be left floating or connected to VSS through a 20-kΩ resistor.
32 BAT P Primary power supply input pin
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output