SLUSBB1B December   2012  – June 2016


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics Curves
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Fundamentals
      2. 7.1.2 Wireless Power Consortium (WPC)
      3. 7.1.3 Power Transfer
      4. 7.1.4 Communication
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Dynamic Power Limiting™
      2. 7.3.2  Option Select Pin
      3. 7.3.3  LED Indication Modes
      4. 7.3.4  Parasitic Metal Object Detect (PMOD) and Foreign Object Detection (FOD)
      5. 7.3.5  Shut Down via External Thermal Sensor or Trigger
      6. 7.3.6  Fault Handling and Indication
      7. 7.3.7  Power Transfer Start Signal
      8. 7.3.8  Power-On Reset
      9. 7.3.9  External Reset, RESET Pin
      10. 7.3.10 Trickle Charge and CS100
      11. 7.3.11 Current Monitoring Requirements
      12. 7.3.12 Overcurrent Protection
      13. 7.3.13 MSP430G2001 Low Power Supervisor
        1. MSP430 Low Power Supervisor Details
      14. 7.3.14 All Unused Pins
  8. Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Detailed Design Procedure
        1. Coils and Matching Capacitors
        2. Input Regulator
        3. Power Train
        4. Low Power Supervisor
        5. Disabling Low Power Supervisor Mode
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Layout

9.1 Layout Guidelines

A good PCB layout is critical to proper system operation and due care should be taken. There are many references on proper PCB layout techniques.

Generally speaking, the system layout will require a 4-layer PCB layout, although a 2-layer PCB layout can be achieved. A proven and recommended approach to the layer stack-up has been:

  • Layer 1, component placement and as much ground plane as possible.
  • Layer 2, clean ground.
  • Layer 3, finish routing.
  • Layer 4, clean ground.

Thus, the circuitry is virtually sandwiched between grounds. This minimizes EMI noise emissions and also provides a noise free voltage reference plane for device operation.

Keep as much copper as possible. Make sure the bq500211A GND pins and the power pad have a continuous flood connection to the ground plane. The power pad should also be stitched to the ground plane, which also acts as a heat sink for the bq500211A. A good GND reference is necessary for proper bq500211A operation, such as analog-digital conversion, clock stability and best overall EMI performance.

Separate the analog ground plane from the power ground plane and use only one tie point to connect grounds. Having several tie points defeats the purpose of separating the grounds.

The COMM return signal from the resonant tank should be routed as a differential pair. This is intended to reduce stray noise induction. The frequencies of concern warrant low-noise analog signaling techniques, such as differential routing and shielding, but the COMM signal lines do not need to be impedance matched.

Typically a single chip controller solution with integrated power FET and synchronous rectifier will be used. To create a tight loop, pull in the buck inductor and power loop as close as possible. Likewise, the power-train, full-bridge components should be pulled together as tight as possible. See the bq500211AEVM-045, bqTESLA Wireless Power TX EVM User's Guide (SLVU536) for layout examples.