SLUSBB1B December 2012 – June 2016
A good PCB layout is critical to proper system operation and due care should be taken. There are many references on proper PCB layout techniques.
Generally speaking, the system layout will require a 4-layer PCB layout, although a 2-layer PCB layout can be achieved. A proven and recommended approach to the layer stack-up has been:
Thus, the circuitry is virtually sandwiched between grounds. This minimizes EMI noise emissions and also provides a noise free voltage reference plane for device operation.
Keep as much copper as possible. Make sure the bq500211A GND pins and the power pad have a continuous flood connection to the ground plane. The power pad should also be stitched to the ground plane, which also acts as a heat sink for the bq500211A. A good GND reference is necessary for proper bq500211A operation, such as analog-digital conversion, clock stability and best overall EMI performance.
Separate the analog ground plane from the power ground plane and use only one tie point to connect grounds. Having several tie points defeats the purpose of separating the grounds.
The COMM return signal from the resonant tank should be routed as a differential pair. This is intended to reduce stray noise induction. The frequencies of concern warrant low-noise analog signaling techniques, such as differential routing and shielding, but the COMM signal lines do not need to be impedance matched.
Typically a single chip controller solution with integrated power FET and synchronous rectifier will be used. To create a tight loop, pull in the buck inductor and power loop as close as possible. Likewise, the power-train, full-bridge components should be pulled together as tight as possible. See the bq500211AEVM-045, bqTESLA Wireless Power TX EVM User's Guide (SLVU536) for layout examples.