SWRS187D August   2016  – July 2019 CC2650MODA

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Module Pin Diagram
    2. 4.2 Pin Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
    5. 5.5  General Characteristics
    6. 5.6  Antenna
    7. 5.7  1-Mbps GFSK (Bluetooth low energy) – RX
    8. 5.8  1-Mbps GFSK (Bluetooth low energy) – TX
    9. 5.9  IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – RX
    10. 5.10 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX
    11. 5.11 24-MHz Crystal Oscillator (XOSC_HF)
    12. 5.12 32.768-kHz Crystal Oscillator (XOSC_LF)
    13. 5.13 48-MHz RC Oscillator (RCOSC_HF)
    14. 5.14 32-kHz RC Oscillator (RCOSC_LF)
    15. 5.15 ADC Characteristics
    16. 5.16 Temperature Sensor
    17. 5.17 Battery Monitor
    18. 5.18 Continuous Time Comparator
    19. 5.19 Low-Power Clocked Comparator
    20. 5.20 Programmable Current Source
    21. 5.21 DC Characteristics
    22. 5.22 Thermal Resistance Characteristics for MOH Package
    23. 5.23 Timing Requirements
    24. 5.24 Switching Characteristics
    25. 5.25 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Main CPU
    4. 6.4  RF Core
    5. 6.5  Sensor Controller
    6. 6.6  Memory
    7. 6.7  Debug
    8. 6.8  Power Management
    9. 6.9  Clock Systems
    10. 6.10 General Peripherals and Modules
    11. 6.11 System Architecture
    12. 6.12 Certification
      1. 6.12.1 Regulatory Information Europe
      2. 6.12.2 Federal Communications Commission Statement
      3. 6.12.3 Canada, Industry Canada (IC)
      4. 6.12.4 Japan (JATE ID)
    13. 6.13 End Product Labeling
    14. 6.14 Manual Information to the End User
    15. 6.15 Module Marking
  7. 7 Application, Implementation, and Layout
    1. 7.1 Application Information
      1. 7.1.1 Typical Application Circuit
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
  8. 8 Environmental Requirements and Specifications
    1. 8.1 PCB Bending
    2. 8.2 Handling Environment
      1. 8.2.1 Terminals
      2. 8.2.2 Falling
    3. 8.3 Storage Condition
      1. 8.3.1 Moisture Barrier Bag Before Opened
      2. 8.3.2 Moisture Barrier Bag Open
    4. 8.4 Baking Conditions
    5. 8.5 Soldering and Reflow Condition
  9. 9 Device and Documentation Support
    1. 9.1  Device Nomenclature
    2. 9.2  Tools and Software
    3. 9.3  Documentation Support
    4. 9.4  Texas Instruments Low-Power RF Website
    5. 9.5  Low-Power RF eNewsletter
    6. 9.6  Community Resources
    7. 9.7  Additional Information
    8. 9.8  Trademarks
    9. 9.9  Electrostatic Discharge Caution
    10. 9.10 Export Control Notice
    11. 9.11 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information
    2. 10.2 PACKAGE OPTION ADDENDUM
      1. 10.2.1 PACKAGING INFORMATION
    3. 10.3 PACKAGE MATERIALS INFORMATION
      1. 10.3.1 TAPE AND REEL INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • MOH|29
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.15 ADC Characteristics

Tc = 25°C, VDD = 3.0 V and voltage scaling enabled, unless otherwise noted (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDD V
Resolution 12 Bits
Sample rate 200 ksps
Offset Internal 4.3-V equivalent reference(2) 2 LSB
Gain error Internal 4.3-V equivalent reference(2) 2.4 LSB
DNL(4) Differential nonlinearity >–1 LSB
INL(5) Integral nonlinearity ±3 LSB
ENOB Effective number of bits Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		 9.8 Bits
VDD as reference, 200 ksps, 9.6-kHz input tone 10
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		 11.1
THD Total harmonic distortion Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		 –65 dB
VDD as reference, 200 ksps, 9.6-kHz input tone –69
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		 –71
SINAD and SNDR Signal-to-noise and distortion ratio Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		 60 dB
VDD as reference, 200 ksps, 9.6-kHz input tone 63
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksps, 300-Hz input tone		 69
SFDR Spurious-free dynamic range Internal 4.3-V equivalent reference(2), 200 ksps,
9.6-kHz input tone		 67 dB
VDD as reference, 200 ksps, 9.6-kHz input tone 72
Internal 1.44-V reference, voltage scaling disabled, 32 samples average, 200 ksps, 300-Hz input tone 73
Conversion time Serial conversion, time-to-output, 24-MHz clock 50 clock-cycles
Current consumption Internal 4.3-V equivalent reference(2) 0.66 mA
Current consumption VDD as reference 0.75 mA
Reference voltage Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS™ API to include the gain or offset compensation factors stored in FCFG1. 4.3(2)(3) V
Reference voltage Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API to include the gain or offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3 V) as follows: Vref = 4.3 V × 1408 / 4095 1.48 V
Reference voltage VDD as reference (Also known as RELATIVE) (input voltage scaling enabled) VDD V
Reference voltage VDD as reference (Also known as RELATIVE) (input voltage scaling disabled) VDD / 2.82(3) V
Input Impedance 200 ksps, voltage scaling enabled. Capacitive input, input impedance depends on sampling frequency and sampling time >1 MΩ
(1) Using IEEE Std 1241™-2010 for terminology and test methods.
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V.
(3) Applied voltage must be within absolute maximum ratings (see Section 5.1) at all times.
(4) No missing codes. Positive DNL typically varies from +0.3 to +3.5 depending on device, see Figure 5-24.
(5) For a typical example, see Figure 5-25.