SWAS034A February   2017  – May 2021 CC3120


  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagrams
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
    3. 7.3 Connections for Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary
    6. 8.6  TX Power and IBAT versus TX Power Level Settings
    7. 8.7  Brownout and Blackout Conditions
    8. 8.8  Electrical Characteristics (3.3 V, 25°C)
    9. 8.9  WLAN Receiver Characteristics
    10. 8.10 WLAN Transmitter Characteristics
    11. 8.11 WLAN Filter Requirements
      1. 8.11.1 WLAN Filter Requirements
    12. 8.12 Thermal Resistance Characteristics
      1. 8.12.1 Thermal Resistance Characteristics for RGK Package
    13. 8.13 Reset Requirement
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Power Supply Sequencing
      2. 8.14.2 Device Reset
      3. 8.14.3 Reset Timing
        1. nRESET (32-kHz Crystal)
        2. First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
        3. nRESET (External 32-kHz)
          1. First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz)
      4. 8.14.4 Wakeup From HIBERNATE Mode
        1. nHIB Timing Requirements
      5. 8.14.5 Clock Specifications
        1. Slow Clock Using Internal Oscillator
          1. RTC Crystal Requirements
        2. Slow Clock Using an External Clock
          1. External RTC Digital Clock Requirements
        3. Fast Clock (Fref) Using an External Crystal
          1. WLAN Fast-Clock Crystal Requirements
        4. Fast Clock (Fref) Using an External Oscillator
          1. External Fref Clock Requirements (–40°C to +85°C)
      6. 8.14.6 Interfaces
        1. Host SPI Interface Timing
          1. Host SPI Interface Timing Parameters
        2. Flash SPI Interface Timing
          1. Flash SPI Interface Timing Parameters
    15. 8.15 External Interfaces
      1. 8.15.1 SPI Flash Interface
        1. SPI Flash Interface
      2. 8.15.2 SPI Host Interface
        1. SPI Host Interface
      3. 8.15.3 Host UART Interface
        1. SimpleLink™ UART Configuration
        2. 5-Wire UART Topology
        3. 4-Wire UART Topology
        4. 3-Wire UART Topology
  9. Detailed Description
    1. 9.1 Device Features
      1. 9.1.1 WLAN
      2. 9.1.2 Network Stack
      3. 9.1.3 Security
      4. 9.1.4 Host Interface and Driver
      5. 9.1.5 System
    2. 9.2 Power-Management Subsystem
      1. 9.2.1 VBAT Wide-Voltage Connection
      2. 9.2.2 Preregulated 1.85V
    3. 9.3 Low-Power Operating Modes
      1. 9.3.1 Low-Power Deep Sleep
      2. 9.3.2 Hibernate
      3. 9.3.3 Shutdown
    4. 9.4 Memory
      1. 9.4.1 External Memory Requirements
    5. 9.5 Restoring Factory Default Configuration
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 Typical Application—CC3120R Wide-Voltage Mode
      2. 10.1.2 Typical Application Schematic—CC3120R Preregulated, 1.85-V Mode
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. Design Considerations
      3. 10.2.3 Clock Interfaces
      4. 10.2.4 Digital Input and Output
      5. 10.2.5 RF Interface
  11. 11Device and Documentation Support
    1. 11.1 Development Tools and Software
    2. 11.2 Firmware Updates
    3. 11.3 Device Nomenclature
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Attributes

Table 7-1 describes the CC3120R pins.


If an external device drives a positive voltage to signal pads when the CC3120R device is not powered, DC current is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3120R device can occur. To prevent current draw, TI recommends one of the following:

  • All devices interfaced to the CC3120R device must be powered from the same power rail as the CC3120R device.
  • Use level shifters between the CC3120R device and any external devices fed from other independent rails.
  • The nRESET pin of the CC3120R device must be held low until the VBAT supply to the device is driven and stable.
Table 7-1 Pin Attributes
2nHIBHi-ZIHibernate signal input to the NWP subsystem (active low). This is connected to the MCU GPIO. If the GPIO from the MCU can float while the MCU enters low power, consider adding a pullup resistor on the board to avoid floating.
3ReservedHi-ZReserved for future use
5HOST_SPI_CLKHi-ZIHost interface SPI clock
6HOST_SPI_MOSIHi-ZIHost interface SPI data input
7HOST_SPI_MISOHi-ZOHost interface SPI data output
8HOST_SPI_nCSHi-ZIHost interface SPI chip select (active low)
9VDD_DIG1Hi-ZPowerDigital core supply (1.2 V)
10VIN_IO1Hi-ZPowerI/O supply
11FLASH_SPI_CLKHi-ZOSerial Flash interface: SPI clock
12FLASH_SPI_MOSIHi-ZOSerial Flash interface: SPI data out
13FLASH _SPI_MISOHi-ZISerial Flash interface: SPI data in (active high)
14FLASH _SPI_CSHi-ZOSerial Flash interface: SPI chip select
(active low)
15HOST_INTRHi-ZOInterrupt output (active high)
19ReservedHi-ZConnect a 100-kΩ pulldown resistor to ground.
21SOP2/TCXO_ENHi-ZOControls restore to default mode. Enable signal for external TCXO. Add a 10-kΩ pulldown resistor to ground.
22WLAN_XTAL_NHi-ZAnalogConnect the WLAN 40-MHz crystal here.
23WLAN_XTAL_PHi-ZAnalogConnect the WLAN 40-MHz crystal here.
24VDD_PLLHi-ZPowerInternal PLL power supply (1.4-V nominal)
25LDO_IN2Hi-ZPowerInput to internal LDO
29ReservedHi-ZOReserved for future use
32nRESETHi-ZIRESET input for the device. Active low input. Use RC circuit (100 k || 0.1 µF) for power on reset (POR).
33VDD_PA_INHi-ZPowerPower supply for the RF power amplifier (PA)
34SOP1Hi-ZSOP[2:0] used for factory restore. Add 100-kΩ pulldown to ground. See .
35SOP0Hi-ZSOP[2:0] used for factory restore. Add 100-kΩ pulldown to ground. See .
36LDO_IN1Hi-ZPowerInput to internal LDO
37VIN_DCDC_ANAHi-ZPowerPower supply for the DC/DC converter for analog section
38DCDC_ANA_SWHi-ZPowerAnalog DC/DC converter switch output
39VIN_DCDC_PAHi-ZPowerPA DC/DC converter input supply
40DCDC_PA_SW_PHi-ZPowerPA DC/DC converter switch output +ve
41DCDC_PA_SW_NHi-ZPowerPA DC/DC converter switch output –ve
42DCDC_PA_OUTHi-ZPowerPA DC/DC converter output. Connect the output capacitor for DC/DC here.
43DCDC_DIG_SWHi-ZPowerDigital DC/DC converter switch output
44VIN_DCDC_DIGHi-ZPowerPower supply input for the digital DC/DC converter
45DCDC_ANA2_SW_PHi-ZPowerAnalog2 DC/DC converter switch output +ve
46DCDC_ANA2_SW_NHi-ZPowerAnalog2 DC/DC converter switch output –ve
47VDD_ANA2Hi-ZPowerAnalog2 power supply input
48VDD_ANA1Hi-ZPowerAnalog1 power supply input
49VDD_RAMHi-ZPowerPower supply for the internal RAM
50UART1_nRTSHi-ZOUART host interface (active low)
51RTC_XTAL_PHi-ZAnalog32.768-kHz XTAL_P or external CMOS level clock input
52RTC_XTAL_NHi-ZAnalog32.768-kHz XTAL_N or 100-kΩ external pullup for external clock
54VIN_IO2Hi-ZPowerI/O power supply. Same as battery voltage.
55UART1_TXHi-ZOUART host interface. Connect to test point on prototype for Flash programming.
56VDD_DIG2Hi-ZPowerDigital power supply (1.2 V)
57UART1_RXHi-ZIUART host interface; connect to test point on prototype for Flash programming.
60TEST_60Hi-ZOTest signal; connect to an external test point.
61UART1_nCTSHi-ZIUART host interface (active low)
62TEST_62Hi-ZOTest signal; connect to an external test point.
GNDPowerGround tab used as thermal and electrical ground
I = Input
O = Output
RF = radio frequency
I/O = bidirectional