SCHS248C November 1998 – April 2025 CD54AC257 , CD54ACT257 , CD74AC257 , CD74ACT257 , CD74ACT258
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Figure 3-1 CD54AC257, CD54ACT257 J
Package; CD74AC257, CD74ACT257, CD74ACT258 D, N, or PW Package; 16-Pin SOIC
PDIP, or TSSOP (Top View)
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| S | 1 | I | Select |
| 1I0 | 2 | I | Channel 1 Input 0 |
| 1I1 | 3 | I | Channel 1 Input 1 |
| 1Y | 4 | O | Channel 1 Output |
| 2I0 | 5 | I | Channel 2 Input 0 |
| 2I1 | 6 | I | Channel 2 Input 1 |
| 2Y | 7 | O | Channel 2 Output |
| GND | 8 | G | Ground |
| 3Y | 9 | O | Channel 3 Output |
| 3I1 | 10 | I | Channel 3 Input 1 |
| 3I0 | 11 | I | Channel 3 Input 0 |
| 4Y | 12 | O | Channel 4 Output |
| 4I1 | 13 | I | Channel 4 Input 1 |
| 4I0 | 14 | I | Channel 4 Input 0 |
| OE | 15 | I | Output Enable |
| VCC | 16 | P | Positive Supply |
| Thermal Pad(2) | – | The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply | |