SCHS149G November   1998  – January 2025 CD54HC147 , CD74HC147 , CD74HCT147

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Thermal Information
    4. 4.4 Electrical Characteristics
    5. 4.5 Switching Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.4 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC (V) 25°C -40°C to 85°C -55°C to 125°C UNIT
VI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
VIH High-level input voltage 2 1.5 1.5 1.5 V
4.5 3.15 3.15 3.15 V
6 4.2 4.2 4.2 V
VIL Low-level input voltage 2 0.5 0.5 0.5 V
4.5 1.35 1.35 1.35 V
6 1.8 1.8 1.8 V
VOH High-level output voltage

CMOS loads

 VIH or VIL -0.02 2 1.9 1.9 1.9 V
-0.02 4.5 4.4 4.4 4.4 V
-0.02 6 5.9 5.9 5.9 V
High-level output voltage

TTL loads

 –4 4.5 3.98 3.84 3.7 V
–5.2 6 5.48 5.34 5.2 V
VOL Low-level output voltage

CMOS loads

 VIH or VIL 0.02 2 0.1 0.1 0.1 V
0.02 4.5 0.1 0.1 0.1 V
0.02 6 0.1 0.1 0.1 V
Low-level output voltage

TTL loads

 4 4.5 0.26 0.33 0.4 V
5.2 6 0.26 0.33 0.4 V
II Input leakage current VCC or GND 6 ±0.1 ±1 ±1 µA
ICC Quiescent device current VCC or GND 0 6 8 80 160 µA
HCT TYPES
VIH High-level input voltage 4.5 to 5.5 2 2 2 V
VIL Low-level input voltage 4.5 to 5.5 0.8 0.8 0.8 V
VOH High-level output voltage

CMOS loads

 VIH or VIL -0.02 4.5 4.4 4.4 4.4 V
High-level output voltage

TTL loads

 -4 4.5 3.98 3.84 3.7 V
VOL Low-level output voltage

CMOS loads

 VIH or VIL 0.02 4.5 0.1 0.1 0.1 V
Low-level output voltage

TTL

 4 4.5 0.26 0.33 0.4 V
II Input leakage current VCC and GND 0 5.5 ±0.1 ±1 ±1 µA
ICC Quiescent device current VCC or GND 0 5.5 8 80 160 µA
∆ICC(1) Additional quiescent device current per input pin: 1 Unit Load VCC -2.1 4.5 to 5.5 100 360 450 490 µA
(1) VI = VIH or VIL, unless otherwise noted.

HCT Input Loading Table

INPUT UNIT LOADS(1)
I1, I2, I3, I6, I7 1.1
I4, I5, I8, I9 1.5
(1) Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.