SCHS371G November   2009  – November 2022 CDC3RL02

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low Additive Noise
      2. 8.3.2 Regulated 1.8-V Externally Available I/O Supply
      3. 8.3.3 Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP Package
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Clock Squarer
      2. 9.1.2 Output Stage
      3. 9.1.3 LDO
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision F (August 2019) to Revision G (November 2022)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed MCLK_IN frequency maximum value from: 54 MHz to: 80 MHzGo
  • Changed the x-axis range in Figure 7-3 Go
  • Moved the Power Supply Recommendations and Layout sections to the Application and Implementation sectionGo

Changes from Revision E (August 2018) to Revision F (August 2019)

  • Changed MCLK_IN frequency maximum value from: 52 MHz to: 54 MHzGo

Changes from Revision D (April 2017) to Revision E (August 2018)

  • Changed VLDO test conditions to VIH conditions in the Electrical Characteristics table Go
  • Added a tablenote to the Function Table Go
  • Added content to the LDO section Go
  • Changed the last sentence in the Detailed Design Procedure section Go

Changes from Revision C (January 2016) to Revision D (April 2017)

  • Updated clock request descriptions in the Pin Functions tableGo
  • Added Receiving Notification of Documentation Updates sectionGo

Changes from Revision B (December 2015) to Revision C (January 2016)

Changes from Revision A (September 2015) to Revision B (November 2015)

  • Added Thermal Information table, Overview, Feature Description section, Power Supply Recommendations section, and Layout sectionGo

Changes from Revision * (November 2009) to Revision A (September 2015)

  • Formatted document to new standards.Go