SCAS862G November   2008  – July 2016 CDCE62005

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements
    6. 6.6 SPI Bus Timing Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
      1. 8.2.1 Interface and Control Block
      2. 8.2.2 Input Block
      3. 8.2.3 Output Block
      4. 8.2.4 Clock Divider Module 0-4
      5. 8.2.5 Synthesizer Block
      6. 8.2.6 Computing The Output Frequency
    3. 8.3 Feature Description
      1. 8.3.1  Phase Noise Analysis
      2. 8.3.2  Output To Output Isolation
      3. 8.3.3  Device Control
      4. 8.3.4  External Control Pins
      5. 8.3.5  Input Block
        1. 8.3.5.1  Universal Input Buffers (UIB)
        2. 8.3.5.2  LVDS Fail Safe Mode
        3. 8.3.5.3  Smart Multiplexer Controls
        4. 8.3.5.4  Smart Multiplexer Auto Mode
        5. 8.3.5.5  Smart Multiplexer Dividers
        6. 8.3.5.6  Output Block
        7. 8.3.5.7  Output Multiplexer Control
        8. 8.3.5.8  Output Buffer Control
        9. 8.3.5.9  Output Buffer Control - LVCMOS Configurations
        10. 8.3.5.10 Output Dividers
        11. 8.3.5.11 Digital Phase Adjust
        12. 8.3.5.12 Phase Adjust Example
        13. 8.3.5.13 Valid Register Settings for Digital Phase Adjust Blocks
        14. 8.3.5.14 Output Synchronization
        15. 8.3.5.15 Auxiliary Output
        16. 8.3.5.16 Synthesizer Block
        17. 8.3.5.17 Input Divider
        18. 8.3.5.18 Feedback and Feedback Bypass Divider
          1. 8.3.5.18.1 VCO Select
          2. 8.3.5.18.2 Prescaler
          3. 8.3.5.18.3 Charge Pump Current Settings
          4. 8.3.5.18.4 Loop Filter
        19. 8.3.5.19 Internal Loop Filter Component Configuration
        20. 8.3.5.20 External Loop Filter Component Configuration
      6. 8.3.6  Digital Lock Detect
      7. 8.3.7  Crystal Input Interference
      8. 8.3.8  VCO Calibration
      9. 8.3.9  Startup Time Estimation
      10. 8.3.10 Analog Lock Detect
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fan-Out Buffer
      2. 8.4.2 Clock Generator
      3. 8.4.3 Jitter Cleaner - Mixed Mode
        1. 8.4.3.1 Clocking ADCs with the CDCE62005
        2. 8.4.3.2 CDCE62005 SERDES Startup Mode
    5. 8.5 Programming
      1. 8.5.1 Interface and Control Block
        1. 8.5.1.1 Serial Peripheral Interface (SPI)
        2. 8.5.1.2 CDCE62005 SPI Command Structure
        3. 8.5.1.3 SPI Interface Master
        4. 8.5.1.4 SPI Consecutive Read/Write Cycles to the CDCE62005
        5. 8.5.1.5 Writing to the CDCE62005
        6. 8.5.1.6 Reading from the CDCE62005
        7. 8.5.1.7 Writing to EEPROM
      2. 8.5.2 Device Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers: Register 0 Address 0x00
      2. 8.6.2 Device Registers: Register 1 Address 0x01
      3. 8.6.3 Device Registers: Register 2 Address 0x02
      4. 8.6.4 Device Registers: Register 3 Address 0x03
      5. 8.6.5 Device Registers: Register 4 Address 0x04
      6. 8.6.6 Device Registers: Register 5 Address 0x05
      7. 8.6.7 Device Registers: Register 6 Address 0x06
      8. 8.6.8 Device Registers: Register 7 Address 0x07
      9. 8.6.9 Device Registers: Register 8 Address 0x08
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Frequency Synthesizer
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Documentation Support
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Frequency Synthesizer

As shown in Figure 47, the CDCE62005 has internal dividers, twin onboard VCOs, a phase frequency detector, charge pump, partially internal loop filter, and LVPECL/LVDS/LVCMOS input and output buffers, all of which completes a PLL. Through the PLL operation, the VCO clock synchronizes with the reference clock input and ultimately with all clock outputs. All outputs are completely synchronized in terms of phase and frequency with the reference clock input. When powering up from the EEPROM, the SYNC signal synchronizes outputs after device power-up.

See SCAA096 for a detailed description of the application configuration.

9.2 Typical Application

CDCE62005 settings_multiple_freq_synth_example_SCAS862.png Figure 47. CDCE62005 Settings for Multiple Frequency Synthesis Example

9.2.1 Design Requirements

Assume a typical application, where a total of two 156.25-MHz LVPECL, two 125-MHz LVDS, and two 25-MHz LVCMOS output clocks are desired and should be phase-locked to a single back-plane input reference clock of 25 MHz. The goal of this example is to identify the input (M), prescaler (N), feedback (FB), and output (P) divider values, the VCO frequency to lock to, and the other related PLL settings needed to derive the different output frequencies from the common input and VCXO frequencies. Follow the steps outlined in Detailed Design Procedure to achieve this goal.

9.2.2 Detailed Design Procedure

Step 1. From Figure 47, it can be inferred that the relationship between the output frequency and the input frequency is described by these equations,

where:

Equation 17. FVCO = FOUT ´ P ´ N

provided that:

Equation 18. 80 kHz < (FIN/M) < 40 MHz

and:

Equation 19. 1750 MHz < (FOUT ´ P ´ N) < 2350 MHz

Step 2. Keep in mind the following while satisfying the equations in Step 1:

  • The P divider can be chosen to be 1, 2, 3, 4, 5, up to 80
  • The internal VCO range is from 1.75 GHz to 2.35 GHz
  • The input (M) and prescaler (N) dividers can be chosen from Table 22 and Table 26.
  • The FB divider can be chosen from the values in Table 23 and Table 24.

Step 3. Given multiple desired output frequencies and the input frequency, the first step would be to establish M, N, and FB divider values for different P divider settings to satisfy these equations:

Equation 20. FIN = FOUT1 x (M x P1) / (N x FB)
Equation 21. FIN = FOUT2 x (M x P2) / (N x FB)
Equation 22. FIN = FOUT3 x (M x P3) / (N x FB)
Equation 23. FIN = FOUT4 x (M x P4) / (N x FB)
Equation 24. FIN = FOUT5 x (M x P5) / (N x FB)
Equation 25. (FVCO/ N) = FOUT1 x P1 = FOUT2 x P2 = FOUT3 x P3 = FOUT4 x P4 = FOUT5 x P5

Such that these parameters are valid:

  • The common PFD frequency is always less than 40 MHz.
  • The VCXO frequency is the same for deriving all outputs.

Using the example to derive these outputs, it can be seen that there is not an output divider (P5) that will generate a 25-MHz output. However, the output MUX value of output 5 can be chosen to directly bypass the 25-MHz input clock to output 5. Therefore, in order to use a common VCO frequency, the P dividers to be used are:

  • P1 = 4
  • P2 = 4
  • P3 = 5
  • P4 = 5
  • P5 = 1

The common VCO frequency is 1875 MHz and is VCO1. The output MUX for outputs 1 to 4 are set to the PLL/VCO outputs. Moreover, the FB divider to be used is:

Equation 26. FB = 100

The N divider to be used is:

Equation 27. N = 3

These values ensure that the (FIN/M) ratio is within 40 MHz and is set at 6.25 MHz. Thus, the M divider to be used is:

Equation 28. M = 4

Figure 47 illustrates this configuration.

Step 4:

The PLL loop bandwidth of the CDCE62005 is recommended to be set according to the phase noise profile of its reference input and the phase noise profile of the onboard VCO clock. It is recommended to set the PLL loop bandwidth as the crossover point of the reference input phase noise and the phase noise of the VCO clock. When the input clock is clean and any near-frequency offsets are better than the VCO clock, it is beneficial for the PLL bandwidth to be set at several hundred kHz as determined by the crossover point. Figure 48 shows a typical 400-kHz Loop filter.

CDCE62005 on_chip_loop_filter_circuit_400mhz_scas862.png Figure 48. On-Chip Loop Filter Circuit for 400-kHz Loop Bandwidth
(Loop Settings in Figure 47, CP Current at 3.5mA)

9.2.3 Application Curves

CDCE62005 output_12_scas862.png
Figure 49. Output 1/2 = 156.25MHz LVPECL
RMS Jitter is 520 fsec (10 kHz to 20 MHz)
CDCE62005 output_5_scas862.png
Figure 51. Output 5 = 25MHz LVCMOS
RMS Jitter is 261 fsec (10 kHz to 5 MHz)
CDCE62005 output_34_125mhz_inverted_scas862_test.png
Figure 50. Output 3/4 = 125MHz LVDS
RMS Jitter is 540 fsec (10 kHz to 20 MHz)