5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO
Product details
Parameters
Package | Pins | Size
Features
- Superior Performance:
- Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
FC = 100 MHz - Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
FC = 100 MHz
- Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
- Flexible Frequency Planning:
- 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
- Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
- Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
- Output Frequency up to 1.5 GHz in Fan-Out Mode
- Independent Coarse Skew Control on all Outputs
- High Flexibility:
- Integrated EEPROM Determines Device Configuration at Power-up
- Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
- 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
- –40°C to +85°C Temperature Range
Description
The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).
The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.
The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Frequency Synthesizer with PLL/VCO and Partially Integrated Loop Filter.
- Fully Configurable Outputs Including Frequency, Output Format, and Output Skew.
- Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs.
- Multiple Operational Modes Include Clock Generation via Crystal (...)
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Features
Description
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Features
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Features
- Comprehensive test capability for the DAC3283 for IF and RF outputs
- Direct connection to TSW1400EVM signal generator
- Includes CDCE62005 for clock generation or jitter cleaning
- Includes TRF3704 for complete transmitter evaluation
- Software support with a full featured GUI for easy testing
- FMC-DAC-Adapter (...)
Description
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Features
- Comprehensive test capability for the DAC3482
- Direct connection to TSW1400/TSW3100 signal generator
- Includes CDCE62005 for clock generation or jitter cleaning
- Software support with a full featured GUI for easy testing and prototyping
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Description
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Features
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Features
Description
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Features
Software development
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download Using the TMS320C6657 to Implement Efficient OPUS Codec Solution BOM.pdf (191KB) -
download Using the TMS320C6657 to Implement Efficient OPUS Codec Solution PCB.zip (4763KB) -
download Using the TMS320C6657 to Implement Efficient OPUS Codec Solution CAD Files.zip (1728KB) -
download Using the TMS320C6657 to Implement Efficient OPUS Codec Solution Gerber.zip (9013KB)
Design files
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| VQFN (RGZ) | 48 | View options |
Ordering & quality
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