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CDCE62005

ACTIVE

5/10 outputs clock generator/jitter cleaner with integrated dual VCO

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Data sheet

CDCE62005

ACTIVE
Data sheet Order now

Product details

Function Clock generator Number of outputs 5 Output frequency (max) (MHz) 1175 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
Function Clock generator Number of outputs 5 Output frequency (max) (MHz) 1175 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
VQFN (RGZ) 48 49 mm² 7 x 7
  • Superior Performance:
    • Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
    • Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
  • Flexible Frequency Planning:
    • 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
    • Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
    • Output Frequency up to 1.5 GHz in Fan-Out Mode
    • Independent Coarse Skew Control on all Outputs
  • High Flexibility:
    • Integrated EEPROM Determines Device Configuration at Power-up
    • Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
  • 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
  • –40°C to +85°C Temperature Range
  • Superior Performance:
    • Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
    • Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
  • Flexible Frequency Planning:
    • 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
    • Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
    • Output Frequency up to 1.5 GHz in Fan-Out Mode
    • Independent Coarse Skew Control on all Outputs
  • High Flexibility:
    • Integrated EEPROM Determines Device Configuration at Power-up
    • Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
  • 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
  • –40°C to +85°C Temperature Range

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).

The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.

The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).

The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.

The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.
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Technical documentation

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Type Title Date
* Data sheet CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs datasheet (Rev. G) PDF | HTML 23 May 2016
User guide TSW6011EVM Quick Start Guide (Rev. D) 17 Aug 2016
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Application note Clocking Design Guidelines: Unused Pins 19 Nov 2015
Application note Effects of Clock Spur on High Speed DAC Performance (Rev. A) 18 May 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
Application note Effects of Clock Noise on High Speed DAC Performance 08 Nov 2012
Application note Phase Noise Performance and Loop Bandwidth Optimization of CDCE62005 11 Aug 2011
Application note CDCE62005 Application Report 21 Nov 2008
Application note LAN & WAN clock generation and muxing using the CDCE62005 19 Nov 2008
User guide Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz 11 Nov 2008
Application note CDCE62005 Phase Noise and Jitter Cleaning Performance 05 Sep 2008
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCE62005EVM — CDCE62005EVM Evaluation Module

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, (...)
User guide: PDF
Not available on TI.com
Evaluation board

DAC3152EVM — DAC3152 Dual-Channel, 10-Bit, 500-MSPS Digital-to-Analog Converter Evaluation Module

The DAC3152EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 10-bit 500 MSPS DAC3152 digital-to-analog converter (DAC) with 10-byte wide DDR LVDS data input, very low power, size and latency. The EVM provides a flexible environment to test (...)

User guide: PDF
Not available on TI.com
Evaluation board

DAC3162EVM — DAC3162 Dual-Channel, 12-Bit, 500-MSPS Digital-to-Analog Converter Evaluation Module

The DAC3162EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 12-bit 500 MSPS DAC3162 digital-to-analog converter (DAC) with 12-byte wide DDR LVDS data input, very low power, size and latency. The EVM provides a flexible environment to test (...)

User guide: PDF
Not available on TI.com
Evaluation board

DAC3283EVM — DAC3283 Dual-Channel, 16-Bit, 800-MSPS, 1x-4x Interpolating Digital-to-Analog Evaluation Module

The DAC3283EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 16-bit 800 MSPS DAC3283 digital-to-analog converter (DAC) with 8-byte wide DDR LVDS data input, integrated 2x/4x interpolation filters and exceptional linearity at high IFs. The (...)

User guide: PDF
Not available on TI.com
Evaluation board

DAC3482EVM — DAC3482 Dual-Channel, 16-Bit, 1.25-GSPS Digital-to-Analog Converter Evaluation Module

The DAC3482EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' two-channel, ultra-low power, 16-bit, 1.25 GSPS DAC3482 digital-to-analog converter (DAC) with 16-bit or 8-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit (...)

User guide: PDF
Not available on TI.com
Evaluation board

DAC3484EVM — DAC3484 Quad-Channel, 16-Bit, 1.25-GSPS Digital-to-Analog Converter Evaluation Module

The DAC3484EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' four-channel, ultra-low power, 16-bit, 1.25 GSPS DAC3484 digital-to-analog converter (DAC) with 16-bit or 8-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit (...)

User guide: PDF
Not available on TI.com
Evaluation board

DAC34H84EVM — DAC34H84 Quad-Channel, 16-Bit, 1.25-GSPS Digital-to-Analog Converter Evaluation Module

The DAC34H84EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' four-channel, ultra-low power, 16-bit, 1.25 GSPS DAC34H84 digital-to-analog converter (DAC) with 32-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit NCO and (...)

User guide: PDF
Not available on TI.com
Evaluation board

DAC34SH84EVM — DAC34SH84 Quad-Channel, 16-Bit, 1.5-GSPS Digital-to-Analog Converter Evaluation Module

The DAC34SH84EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' four-channel, ultra-low power, 16-bit, 1.5 GSPS DAC34SH84 digital-to-analog converter (DAC) with 32-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit NCO and (...)

User guide: PDF
Not available on TI.com
GUI for evaluation module (EVM)

SLAC557 — TSW6011EVM GUI Installer

Supported products & hardware

Supported products & hardware

Products
Clock generators
CDCE62005 — 5/10 outputs clock generator/jitter cleaner with integrated dual VCO
IQ demodulators
TRF371125 — 0.7 - 4.0 GHz Wide Bandwidth Integrated Direct Down Conversion Receiver
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Support software

SCAC105 — CDCE62005 EVM Control Software Installer

Supported products & hardware

Supported products & hardware

Products
Clock generators
CDCE62005 — 5/10 outputs clock generator/jitter cleaner with integrated dual VCO
Hardware development
Evaluation board
CDCE62005EVM — CDCE62005EVM Evaluation Module
Download options
Simulation model

CDCE62005 IBIS Model (Rev. A)

SCAM051A.ZIP (80 KB) - IBIS Model
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Reference designs

TIDEP0036 — Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution

The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00078 — Direct Down-Conversion System with I/Q Correction

The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
VQFN (RGZ) 48 View options
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