CDCE62005

ACTIVE

5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO

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Product details

Parameters

Function Clock generator Number of outputs 5 Output frequency (Max) (MHz) 1175 VCC core (V) 3.3 VCC out (V) 3.3 Input type LVPECL Output type LVPECL Operating temperature range (C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog open-in-new Find other Clock generators

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other Clock generators

Features

  • Superior Performance:
    • Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
    • Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
      FC = 100 MHz
  • Flexible Frequency Planning:
    • 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
    • Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
    • Output Frequency up to 1.5 GHz in Fan-Out Mode
    • Independent Coarse Skew Control on all Outputs
  • High Flexibility:
    • Integrated EEPROM Determines Device Configuration at Power-up
    • Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
  • 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
  • –40°C to +85°C Temperature Range
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Description

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).

The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.

The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

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Same functionality but is not pin-for-pin or parametrically equivalent to the compared device:
CDCM6208 ACTIVE 2:8 Ultra Low Power, Low Jitter Clock Generator CDCM6208 has higher performance compared to CDCE62005

Technical documentation

= Featured
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Type Title Date
* Datasheet CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs datasheet (Rev. G) May 23, 2016
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017
User guides TSW6011EVM Quick Start Guide (Rev. D) Aug. 17, 2016
Technical articles How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Application notes Clocking Design Guidelines: Unused Pins Nov. 19, 2015
Application notes Effects of Clock Spur on High Speed DAC Performance (Rev. A) May 18, 2015
Selection guides Analog for Xilinx (R) FPGAs Selection Guide - 2015 (Rev. B) Jan. 07, 2015
Technical articles Clocking sampled systems to minimize jitter Jul. 31, 2014
Technical articles Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014
Application notes Effects of Clock Noise on High Speed DAC Performance Nov. 08, 2012
Application notes Phase Noise Performance and Loop Bandwidth Optimization of CDCE62005 Aug. 11, 2011
More literature Clocking the Signal Path: Part 1 [WMV] Sep. 15, 2010
More literature Clocking the Signal Path: Part 2 [WMV] Sep. 15, 2010
More literature Demystifying DRAM Jitter, Part 1: Basics [WMV] Sep. 15, 2010
More literature Demystifying DRAM Jitter, Part 2: DRAM Input Jitter [WMV] Sep. 15, 2010
More literature Demystifying DRAM Jitter, Part 3: DRAM Output Jitter [WMV] Sep. 15, 2010
Application notes CDCE62005 Application Report Nov. 21, 2008
Application notes LAN & WAN clock generation and muxing using the CDCE62005 Nov. 19, 2008
User guides Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz Nov. 11, 2008
Application notes CDCE62005 Phase Noise and Jitter Cleaning Performance Sep. 05, 2008
Application notes CDCE62005 as Clock Solution for High-Speed ADCs Sep. 04, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$199.00
Description
The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the (...)
Features
  • Frequency Synthesizer with PLL/VCO and Partially Integrated Loop Filter.
  • Fully Configurable Outputs Including Frequency, Output Format, and Output Skew.
  • Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs.
  • Multiple Operational Modes Include Clock Generation via Crystal (...)
EVALUATION BOARDS Download
document-generic User guide
Description

The DAC3152EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 10-bit 500 MSPS DAC3152 digital-to-analog converter (DAC) with 10-byte wide DDR LVDS data input, very low power, size and latency. The EVM provides a flexible environment to test (...)

Features
  • Comprehensive test capability for the DAC3152 for IF and RF outputs
  • Direct connection to TSW3100 pattern generator
  • Includes CDCP1803 for clock generation
  • Includes TRF370333 for complete transmitter evaluation
  • Easy setup: software control not required
  • Adapter connector compatible to Xilinx FPGA EVMs with (...)
  • EVALUATION BOARDS Download
    document-generic User guide
    Description

    The DAC3162EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 12-bit 500 MSPS DAC3162 digital-to-analog converter (DAC) with 12-byte wide DDR LVDS data input, very low power, size and latency. The EVM provides a flexible environment to test (...)

    Features
  • Comprehensive test capability for the DAC3162 for IF and RF outputs
  • Direct connection to TSW3100 pattern generator
  • Includes CDCP1803 for clock generation
  • Includes TRF370333 for complete transmitter evaluation
  • Easy setup: software control not required
  • Adapter connector compatible to Xilinx FPGA EVMs with (...)
  • EVALUATION BOARDS Download
    document-generic User guide
    $499.00
    Description

    The DAC3283EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 16-bit 800 MSPS DAC3283 digital-to-analog converter (DAC) with 8-byte wide DDR LVDS data input, integrated 2x/4x interpolation filters and exceptional linearity at high IFs. The EVM (...)

    Features
    • Comprehensive test capability for the DAC3283 for IF and RF outputs
    • Direct connection to TSW1400EVM signal generator
    • Includes CDCE62005 for clock generation or jitter cleaning
    • Includes TRF3704 for complete transmitter evaluation
    • Software support with a full featured GUI for easy testing
    • FMC-DAC-Adapter (...)
    EVALUATION BOARDS Download
    document-generic User guide
    Description

    The DAC3482EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' two-channel, ultra-low power, 16-bit, 1.25 GSPS DAC3482 digital-to-analog converter (DAC) with 16-bit or 8-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit NCO (...)

    Features
    • Comprehensive test capability for the DAC3482
    • Direct connection to TSW1400/TSW3100 signal generator
    • Includes CDCE62005 for clock generation or jitter cleaning
    • Software support with a full featured GUI for easy testing and prototyping
    • FMC-DAC-Adapter card compatible to connect with FMC interconnect (...)
    EVALUATION BOARDS Download
    document-generic User guide
    Description

    The DAC3484EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' four-channel, ultra-low power, 16-bit, 1.25 GSPS DAC3484 digital-to-analog converter (DAC) with 16-bit or 8-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit (...)

    Features
  • Comprehensive test capability for the DAC3484
  • Direct connection to TSW1400/TSW3100 signal generator
  • Includes CDCE62005 for clock generation or jitter cleaning
  • Software support with a full featured GUI for easy testing and prototyping
  • FMC-DAC-Adapter card compatible to connect with FMC interconnect (...)
  • EVALUATION BOARDS Download
    document-generic User guide
    Description

    The DAC34H84EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' four-channel, ultra-low power, 16-bit, 1.25 GSPS DAC34H84 digital-to-analog converter (DAC) with 32-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit NCO and (...)

    Features
  • Comprehensive test capability for the DAC34H84
  • Direct connection to TSW1400/TSW3100 signal generator
  • Includes CDCE62005 for clock generation or jitter cleaning
  • Software support with a full featured GUI for easy testing and prototyping
  • FMC-DAC-Adapter card compatible to connect with FMC interconnect (...)
  • EVALUATION BOARDS Download
    document-generic User guide
    Description

    The DAC34SH84EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' four-channel, ultra-low power, 16-bit, 1.5 GSPS DAC34SH84 digital-to-analog converter (DAC) with 32-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit NCO and (...)

    Features
  • Comprehensive test capability for the DAC34SH84
  • Direct connection to TSW1400/TSW3100 signal generator
  • Includes CDCE62005 for clock generation or jitter cleaning
  • Software support with a full featured GUI for easy testing and prototyping
  • FMC-DAC-Adapter card compatible to connect with FMC interconnect (...)
  • GUIS FOR EVALUATION MODULES (EVM) Download
    SLAC557.ZIP (855 KB)

    Software development

    SUPPORT SOFTWARE Download
    SCAC105E.ZIP (2245 KB)
    SUPPORT SOFTWARE Download
    SCAC105F.ZIP (2471 KB)

    Design tools & simulation

    SIMULATION MODELS Download
    SCAM051A.ZIP (80 KB) - IBIS Model

    Reference designs

    REFERENCE DESIGNS Download
    Reference Design using TMS320C6657 to Implement Efficient OPUS Codec Solution
    TIDEP0036 The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio (...)
    document-generic Schematic document-generic User guide
    REFERENCE DESIGNS Download
    Direct Down-Conversion System with I/Q Correction
    TIDA-00078 The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent I/Q (...)
    document-generic Schematic document-generic User guide

    CAD/CAE symbols

    Package Pins Download
    VQFN (RGZ) 48 View options

    Ordering & quality

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