SNAS705D January   2017  – February 2024 CDCE813-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 I2C Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA and SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 I2C Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Control Terminal Configuration

The CDCE813-Q1 device has three user-definable control terminals (S0, S1, and S2), which allow external control of device settings. They can be programmed to any of the following functions:

  • Spread-spectrum clocking selection → spread type and spread amount selection
  • Frequency selection → switching between any of two user-defined frequencies
  • Output state selection → output configuration and power-down control

The user can predefine up to eight different control settings. Table 7-1 and Table 7-2 explain these settings.

Table 7-1 Control Terminal Definition
EXTERNAL CONTROL BITSPLL1 SETTINGY1 SETTING
Control functionPLL frequency selectionSSC selectionOutput Y2 and Y3 selectionOutput Y1 and power-down selection
Table 7-2 PLL1 Setting (1)
SSCx [3 BITS]CENTERDOWN
SSC SELECTION (CENTER AND DOWN)
0000% (off)0% (off)
001±0.25%–0.25%
010±0.5%–0.5%
011±0.75%–0.75%
100±1.0%–1.0%
101±1.25%–1.25%
110±1.5%–1.5%
111±2.0%–2.0%
(1) Center and down-spread, Frequency0, Frequency1, State0, and State1 are user-definable in PLL1 configuration register.
Table 7-3 PLL1 Setting, Frequency Selection (1)
FSxFUNCTION
0Frequency 0
1Frequency 1
(1) Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
Table 7-4 PLL1 Setting, Output Selection (Y2, Y3) (1)
Y2, Y3FUNCTION
0State 0
1State 1
(1) State0 or State1 selection is valid for both outputs of the corresponding PLL module and can be power down, Hi-Z state, low, or active.
Table 7-5 Y1 Setting (1)
Y1FUNCTION
0State 0
1State 1
(1) State0 and State1 are user definable in the generic configuration register and can be power down, Hi-Z state, low, or active.

The S1/SDA and S2/SCL pins of the CDCE813-Q1 device are dual-function pins. In the default configuration, they are defined as SDA and SCL for the serial programming interface. They can be programmed as control pins (S1 and S2) by setting the appropriate bits in the EEPROM.

Note:

Changes to the control register (Bit [6] of byte 02h) have no effect until they are written into the EEPROM.

After the S1/SDA and S2/SCL pins are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA and SCL).

S0 is not a multi-use pin. S0 is a control pin only.