Programmable 1-PLL clock synthesizer and jitter cleaner with 2.5-V and 3.3-V outputs


Product details


Function Single-loop PLL Number of outputs 3 Output frequency (Min) (MHz) 0.07 Output frequency (Max) (MHz) 230 Input type LVCMOS (REF_CLK) Output type LVCMOS Supply voltage (Min) (V) 1.7 Supply voltage (Max) (V) 3.6 Features Integrated EEPROM Operating temperature range (C) -40 to 105 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Clock jitter cleaners & synchronizers


  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 2: –40°C to 105°C ambient operating temperature range
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C6
  • In-system programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8 MHz to 32 MHz
    • Single-ended LVCMOS up to 160 MHz
  • Free selectable output frequency up to 230  MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter (typical 50 ps)
  • 1.8-V device power supply (core voltage)
  • Separate output supply pins: 3.3 V and 2.5 V
  • Flexible clock driver
    • Three user-definable control inputs [S0, S1, S2], for example, SSC selection, frequency switching, output enable, or power down
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth®, WLAN, Ethernet, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0-PPM clock generation
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI ClockPro™ programming software)
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The CDCE813-Q1 device is a modular Phase-locked-loop-based (PLL), low-cost, high-performance, programmable clock synthesizers. They generate up to three output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated configurable PLL.

The CDCE813-Q1 has separate output supply pins, VDDOUT, providing 2.5 V to 3.3 V.

The input accepts an external crystal or LVCMOS clock signal. A selectable on-chip VCXO allows synchronization of the output frequency to an external control signal.

The PLL supports SSC (spread-spectrum clocking) for better electromagnetic interference (EMI) performance.

The device supports nonvolatile EEPROM programming for easy customization of the device to the application. All device settings are programmable through the I2C bus, a 2-wire serial interface.

The CDCE813-Q1 operates in a 1.8-V core environment as well as eliminating the need for additional, independent XTAL oscillators which reduces component count and board size. It operates in a temperature range of –40°C to 105°C.

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Technical documentation

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* Data sheet CDCE813-Q1 Programmable 1-PLL Clock Synthesizer and Jitter Cleaner With 2.5-V and 3.3-V Outputs datasheet (Rev. C) Apr. 26, 2019

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SNAM227.ZIP (27 KB) - IBIS Model
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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

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