SCAS901D September 2010 – November 2017 CDCLVD1212
For reliability and performance reasons, the die temperature must be limited to a maximum of 125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed-circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to ensure adequate heat conduction to of the package. Figure 20 shows a recommended land and via pattern.
The CDCLVD1212 supports high temperatures on the printed-circuit board (PCB) measured at the thermal pad. The system designer must ensure that the maximum junction temperature is not exceeded. ΨJB can allow the system designer to measure the board temperature with a fine gauge thermocouple and back calculate the junction temperature using Equation 1. Note that ΨJB is close to RθJB as 75% to 95% of a device's heat is dissipated by the PCB.
|Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:|
|TPCB = 105°C|
|ΨJB = 9.3°C/W|
|PowerinclTerm = Imax × Vmax = 146 mA × 2.625 V = 383 mW (maximum power consumption including termination resistors)|
|PowerexclTerm = 359 mW (maximum power consumption excluding termination resistors, see Power Consumption of LVPECL and LVDS (SLYT127) for further details)|
|ΔTJ = ΨJB × PowerexclTerm = 9.3°C/W × 359 mW = 3.34°C|
|TJ = ΔTJ + TChassis = 3.34°C + 105°C = 108.34°C (maximum junction temperature of 125°C is not violated)|
Further information can be found at Semiconductor and IC Package Thermal Metrics (SPRA953) and Using Thermal Calculation Tools for Analog Components (SLUA566).