SCAS901D September   2010  – November 2017 CDCLVD1212

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

For reliability and performance reasons, the die temperature must be limited to a maximum of 125°C.

The device package has an exposed pad that provides the primary heat removal path to the printed-circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to ensure adequate heat conduction to of the package. Figure 20 shows a recommended land and via pattern.

11.2 Layout Example

CDCLVD1212 ai_land_pattern_cas886.gif Figure 20. Recommended PCB Layout

11.3 Thermal Considerations

The CDCLVD1212 supports high temperatures on the printed-circuit board (PCB) measured at the thermal pad. The system designer must ensure that the maximum junction temperature is not exceeded. ΨJB can allow the system designer to measure the board temperature with a fine gauge thermocouple and back calculate the junction temperature using Equation 1. Note that ΨJB is close to RθJB as 75% to 95% of a device's heat is dissipated by the PCB.

Equation 1. TJ = TPCB + ( ΨJB × Power)
Example:
Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:
TPCB = 105°C
ΨJB = 9.3°C/W
PowerinclTerm = Imax × Vmax = 146 mA × 2.625 V = 383 mW (maximum power consumption including termination resistors)
PowerexclTerm = 359 mW (maximum power consumption excluding termination resistors, see Power Consumption of LVPECL and LVDS (SLYT127) for further details)
ΔTJ = ΨJB × PowerexclTerm = 9.3°C/W × 359 mW = 3.34°C
TJ = ΔTJ + TChassis = 3.34°C + 105°C = 108.34°C (maximum junction temperature of 125°C is not violated)

Further information can be found at Semiconductor and IC Package Thermal Metrics (SPRA953) and Using Thermal Calculation Tools for Analog Components (SLUA566).