SCAS897A July   2010  – October 2016 CDCLVD1213

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The CDCLVD1213 LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing and termination are required to ensure correct operation of the device and to maximize signal integrity.

The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage different than the output common-mode voltage of the CDCLVD1213, AC-coupling must be used. If the LVDS receiver has internal 100-Ω termination, external termination must be omitted.

8.2 Functional Block Diagram

CDCLVD1213 bd_cas897.gif

8.3 Feature Description

The CDCLVD1213 is a low additive jitter LVDS fan-out buffer that can generate four copies of an LVPECL, LVDS, or CML input, one of which can be frequency divided by a factor of 1, 2, or 4. The CDCLVD1213 can accept reference clock frequencies up to 800 MHz while providing low output skew.

8.4 Device Functional Modes

The divider on output QD can be configured to divide the input frequency by a factor 1, 2, or 4 through the control pin (see Table 1). Unused outputs can be left floating to reduce overall component cost. Both AC- and DC-coupling schemes can be used with the CDCLVD1213 to provide greater system flexibility.

Table 1. Divider Selection Table

DIV DIVIDER RATIO
0 /1
open /2
1 /4

8.4.1 LVDS Output Termination

Unused outputs can be left open without connecting any traces to the output pins.

The CDCLVD1213 can be connected to LVDS receiver inputs with DC- and AC-coupling as shown in Figure 9 and Figure 10 (respectively).

CDCLVD1213 op_DC_term_cas897.gif Figure 9. Output DC Termination
CDCLVD1213 op_AC_term_cas897.gif Figure 10. Output AC Termination (With the Receiver Internally Biased)

8.4.2 Input Termination

The CDCLVD1213 input has an internal 140-Ω termination and can be interfaced with LVDS, LVPECL, or CML drivers. An external 350-Ω resistor (in parallel with the internal 140-Ω termination) is required to interface with a 50-Ω transmission line.

LVDS drivers can be connected to CDCLVD1213 inputs with DC- and AC-coupling as shown in Figure 11 and Figure 12 (respectively). With AC coupling, an external bias voltage (VCC/2) must be provided to the VT pin.

CDCLVD1213 clk_driver_cas897.gif Figure 11. LVDS Clock Driver Connected to CDCLVD1213 Input (DC-Coupled)
CDCLVD1213 LVDS_clk_dvr_cas897.gif Figure 12. LVDS Clock Driver Connected to CDCLVD1213 Input (AC-Coupled)

Figure 13 illustrates how to connect a CML input to the CDCLVD1213 input buffer. The input does not have internal biasing, so external biasing (VCC/2 to VT) is required for AC coupling. If the CML output swing is >1.6 VPP, then signal swing must be reduced to meet VIN, DIF, PP ≤ 1.6 VPP.

CDCLVD1213 CML_clk_dvr_cas897.gif Figure 13. CML Clock Driver Connected to CDCLVD1213 Input

Figure 14 illustrates how to connect an LVPECL input to the CDCLVD1213 input buffer. The input does not have internal biasing, so external biasing (VCC/2 to VT) is required for AC coupling. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 Vpp.

CDCLVD1213 LVPECL_clk_dvr_cas897.gif Figure 14. LVPECL Clock Driver Connected to CDCLVD1213 Input