CDCLVD1213

ACTIVE

Low Jitter, 1:4 Universal-to-LVDS Buffer with Selectable Output Divider

Top

Product details

Parameters

Function Differential Additive RMS jitter (Typ) (fs) 171 Output frequency (Max) (MHz) 800 Number of outputs 4 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 20 Features 1:4 fanout, Selectable divider, Universal inputs Operating temperature range (C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RGT) 16 9 mm² 3 x 3 open-in-new Find other Clock buffers

Features

  • 1:4 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 20 ps (Maximum)
  • Selectable Divider Ratio 1, /2, /4
  • Universal Input Accepts LVDS, LVPECL, and CML
  • 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General-Purpose Clocking

open-in-new Find other Clock buffers

Description

The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution. The input can either be LVDS, LVPECL, or CML.

The CDCLVD1213 contains a high performance divider for one output (QD) which can divide the input clock signal by a factor of 1, 2, or 4.

The CDCLVD1213 is specifically designed for driving 50-Ω transmission lines. The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1213 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

open-in-new Find other Clock buffers
Download
Similar products you might be interested in
open-in-new Compare products
Similar but not functionally equivalent to the compared device:
LMK00301 ACTIVE 3-GHz, 10-Output Differential Fanout Buffer / Level Translator Ultra low additive jitter,1:10 Universal Differential Buffer that can support LVDS

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 2
Type Title Date
* Datasheet CDCLVD1213 1:4 Low Additive Jitter LVDS Buffer With Divider datasheet (Rev. A) Oct. 31, 2016
User guide Low-Additive Jitter, Four-LVDS-Outputs Clock Buffer With Divider EVM Jul. 12, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
149
Description
The CDCLVD1213 is a high-performance, low-additive jitter clock buffer with divider. The device has one differential input with internal 140-ohm differential input termination. The evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVD1213. This fully assembled (...)
Features
  • Easy-to-use evaluation board to fan out low-phase noise clocks
  • Easy device setup
  • Fast configuration
  • Control pin configurable through jumpers
  • Board powered at 2.5 V
  • Differential input clocks
  • Device and EVM support four LVDS outputs

Design tools & simulation

SIMULATION MODEL Download
SLLM087A.ZIP (14 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RGT) 16 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos

Related videos