SCAS859F January   2009  – June 2015 CDCLVP111

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics, LVECL
    6. 6.6 DC Electrical Characteristics, LVPECL
    7. 6.7 AC Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Fanout Buffer for Line Card Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 LVPECL Output Termination
          2. 9.2.1.2.2 Input Termination
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Management
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

7.1 Test Configurations

CDCLVP111 SCAS683-003.gif
A. Output skew is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0, 1,...9) or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9).
B. Part-to-part skew, is calculated as the greater of: The difference between the fastest and the slowest tPLHn (n = 0, 1,...9) across multiple devices or the difference between the fastest and the slowest tPHLn (n = 0, 1,...9) across multiple devices.
C. Typical value measured at ambient when clock input is 155.52 MHz for an integration bandwidth of 20 kHz to 5 MHz.
D. Input conditions: VCM = 1 V, VID = 0.5 V and FIN = 1 GHz.
Figure 2. Waveform for Calculating Both Output and Part-to-Part Skew
CDCLVP111 ai_vo_tr_tf_cas877.pngFigure 3. Output Voltage and Rise and Fall Time
CDCLVP111 typterm_cas859.gifFigure 4. Typical Termination for Output Driver (See the Interfacing Between LVPECL, LVDS, and CML Application Note, SCAA056)
CDCLVP111 ai_test_lvpecl_dc_out_cas880.pngFigure 5. LVPECL Output DC Configuration During Device Test
CDCLVP111 ai_test_lvpecl_ac_out_cas880.pngFigure 6. LVPECL Output AC Configuration During Device Test