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Product details

Parameters

Additive RMS jitter (Typ) (fs) 40 Output frequency (Max) (MHz) 3500 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Features 1:10 fanout Operating temperature range (C) -40 to 85 Rating Catalog Output type LVPECL Input type CML, LVDS, LVPECL, SSTL open-in-new Find other Clock buffers

Package | Pins | Size

LQFP (VF) 32 49 mm² 7 x 7 VQFN (RHB) 32 25 mm² 5.0 x 5.0 open-in-new Find other Clock buffers

Features

  • Distributes One Differential Clock Input Pair
    LVPECL to 10 Differential LVPECL
  • Fully Compatible With LVECL and LVPECL
  • Supports a Wide Supply Voltage Range from
    2.375 V to 3.8 V
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typical 15 ps) for Clock-
    Distribution Applications
    • Additive Jitter Less Than 1 ps
    • Propagation Delay Less Than 350 ps
    • Open Input Default State
    • LVDS, CML, SSTL Input Compatible
  • VBB Reference Voltage Output for Single-Ended
    Clocking
  • Available in a 32-Pin LQFP and QFN Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111,
    ES6111, LVEP111, PTN1111
  • APPLICATIONS
    • Designed for Driving 50-Ω Transmission Lines
    • High Performance Clock Distribution

All other trademarks are the property of their respective owners

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Description

The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND through a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP111 device is characterized for operation from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet CDCLVP111 Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver datasheet (Rev. F) Jun. 30, 2015

Design & development

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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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LQFP (VF) 32 View options
VQFN (RHB) 32 View options

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