SLPS458A Data sheet

SLPS458A December 2013 – August 2014 CSD95373AQ5M

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

DQP|12
- MPSS048A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

T_A = 25°C (unless otherwise noted)

	VALUE		UNIT
	MIN	MAX	UNIT
V_IN to P_GND	–0.3	25	V
V_IN to V_SW	–0.3	25	V
V_IN to V_SW (<10 ns)	–7	27	V
V_SW to P_GND	–0.3	20	V
V_SW to P_GND (<10 ns)	–7	23	V
V_DD to P_GND	–0.3	7	V
ENABLE, PWM, FCCM, TAO to P_GND⁽²⁾	–0.3	V_DD + 0.3	V
BOOT to BOOT_R⁽²⁾	–0.3	V_DD + 0.3	V
Power Dissipation, P_D		12	W
Operating Temperature Range, T_J	–55	150	°C

(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

(2) Should not exceed 7 V.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage Temperature Range		–55	150	°C
V_(ESD)	Electrostatic discharge	Human Body Model (HBM)	–2000	2000	V
V_(ESD)	Electrostatic discharge	Charged Device Model (CDM)	–500	500	V

6.3 Recommended Operating Conditions

T_A = 25° (unless otherwise noted)

		MIN	MAX	UNIT
Gate Drive Voltage, V_DD		4.5	5.5	V
Input Supply Voltage, V_IN⁽¹⁾			16	V
Output Voltage, V_OUT			5.5	V
Continuous Output Current, I_OUT	V_IN = 12 V, V_DD = 5 V, V_OUT = 1.8 V, ƒ_SW = 500 kHz, L_OUT = 0.22 µH⁽²⁾		45	A
Peak Output Current, I_OUT-PK⁽³⁾			67	A
Switching Frequency, ƒ_SW	C_BST = 0.1 µF (min)		2000	kHz
On Time Duty Cycle	ƒ_SW = 1 MHz		85%
Minimum PWM On Time		20		ns
Operating Temperature		–40	125	°C

(1) Operating at high V_IN can create excessive AC voltage overshoots on the switch node (V_SW) during MOSFET switching transients. For reliable operation, the switch node (V_SW) to ground voltage must remain at or below the Absolute Maximum Ratings.

(2) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins.

(3) System conditions as defined in Note 1. Peak Output Current is applied for t_p = 50 µs.

6.4 Thermal Information

T_A = 25°C (unless otherwise noted)

THERMAL METRIC		MIN	TYP	MAX	UNIT
R_θJC	Junction-to-Case Thermal Resistance (Top of package)⁽¹⁾			15	°C/W
R_θJB	Junction-to-Board Thermal Resistance⁽²⁾			2	°C/W

(1) R_θJC is determined with the device mounted on a 1-inch² (6.45-cm²), 2-oz (.071-mm thick) Cu pad on a 1.5-inches x 1.5-inches,
0.06-inch (1.52-mm) thick FR4 board.

(2) R_θJB value based on hottest board temperature within 1 mm of the package.

6.5 Electrical Characteristics

T_A = 25°C, V_DD = POR to 5.5 V (unless otherwise noted)

PARAMETER	CONDITIONS	MIN	TYP	MAX	UNIT
P_LOSS
Power Loss⁽¹⁾	V_IN = 12 V, V_DD = 5 V, V_OUT = 1.2 V, I_OUT = 25 A, ƒ_SW = 500 kHz, L_OUT = 0.22 µH , T_J = 25°C		2.6		W
Power Loss⁽²⁾	V_IN = 12 V, V_DD = 5 V, V_OUT = 1.2 V, I_OUT = 25 A, ƒ_SW = 500 kHz, L_OUT = 0.22 µH , T_J = 125°C		3.3		W
V_IN
V_IN Quiescent Current, I_Q	ENABLE = 0, V_DD = 5 V			10	µA
V_DD
Standby Supply Current, I_DD	ENABLE = 0, PWM = 0			250	µA
Operating Supply Current, I_DD	ENABLE = 5 V, PWM = 50% Duty cycle, ƒ_SW = 500 kHz		16		mA
POWER-ON RESET AND UNDER VOLTAGE LOCKOUT
Power-On Reset, V_DD Rising		3.6		3.9	V
UVLO, V_DD Falling		3.4		3.7	V
Hysteresis		100		250	mV
Startup Delay⁽³⁾	ENABLE = 5 V		6		µs
ENABLE
Logic Level High, V_IH	Schmitt Trigger Input See Figure 12	2			V
Logic Level Low, V_IL				0.8	V
Weak Pulldown Impedance			100		kΩ
Rising Propagation Delay, t_PDH			3		µs
Falling Propagation Delay, t_PDL			30		ns
FCCM⁽²⁾
Logic Level High, V_IH	Schmitt Trigger Input See Figure 14 and Figure 15	2			V
Logic Level Low, V_IL				0.8	V
Weak Pullup Current			5		µA
THERMAL SHUTDOWN⁽²⁾
Start Threshold		150	165		°C
Temperature Hysteresis			25		°C
PWM
I_PWMH	PWM = 5 V		500		µA
I_PWML	PWM = 0		–500		µA
PWM Logic Level High, V_PWMH	C_PWM = 10 pF	2.3	2.5	2.7	V
PWM Logic Level Low, V_PWML		0.7	0.9	1.1	V
PWM Tri-State Open Voltage			1.5		V
PWM to V_SW Propagation Delay, t_PDLH and t_PDHL⁽²⁾			50		ns
Tri-State Shutdown Hold-off Time, t_3HT⁽²⁾			30		ns
Tri-State Shutdown Propagation Delay, t_3SD⁽²⁾			80	160	ns
Tri-State Recovery Propagation Delay, t_3RD⁽²⁾			50	80	ns
Diode Emulation Minimum On Time, t_DEM⁽²⁾			150		ns
BOOTSTRAP SWITCH
Forward Voltage, V_FBOOT	Measured from V_DD to V_BOOT, I_F = 10 mA		200	360	mV
Reverse Leakage, I_RBOOT⁽¹⁾	V_BOOT – V_DD = 20 V		0.15	1	µA
ZERO CROSSING COMPARATOR
LS FET Turn-off Current	Diode Emulation Mode Enabled V_OUT = 1.8 V, L = 150 nH	0		1.1	A
THERMAL ANALOG OUTPUT TAO
Output Voltage at 25°C		0.56	0.60	0.64	V
Output Voltage Temperature Coefficient			8		mV/°C

(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins

(2) Specified by design

(3) POR to V_SW Rising

6.6 Typical Power Stage Device Characteristics

T_J = 125°C, unless stated otherwise. The Typical CSD95373A System Characteristic curves are based on measurements made on a PCB design with dimensions of 4-inches (W) × 3.5-inches (L) × 0.062-inch (T) and 6 copper layers of 1-oz. copper thickness. See the Application and Implementation section for detailed explanation.