SLPS669A March   2017  – January 2018 CSD95490Q5MC

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Typical Power Stage Efficiency and Power Loss
  4. 4Revision History
  5. 5Pin Configuration and Functions
    1.     Pin Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
  7. 7Application Schematic
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Mechanical Drawing
    2. 9.2 Recommended PCB Land Pattern
    3. 9.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DMC|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Recommended Operating Conditions

TA = 25°C (unless otherwise stated)
PARAMETERCONDITIONSMINMAXUNIT
VDD Driver supply voltage 4.5 5.5 V
VIN Input supply voltage(1) 4.5 16 V
VOUT Output voltage 5.5 V
PWM PWM to PGND VDD + 0.3 V
IOUT Continuous output current VIN = 12 V, VDD = 5 V, VOUT = 1.2 V,
ƒSW = 500 kHz(2)		 75 A
IOUT-PK Peak output current(3) 105 A
ƒSW Switching frequency CBST = 0.1 µF (min), VOUT = 2.5 V (max) 1250 kHz
On-time duty cycle ƒSW = 1 MHz 85%
Minimum PWM on-time 20 ns
Operating junction temperature –40 125 °C
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
(2) Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins.
(3) System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs.